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CYF0036V33L-133BGXI Datasheet(PDF) 7 Page - Cypress Semiconductor |
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CYF0036V33L-133BGXI Datasheet(HTML) 7 Page - Cypress Semiconductor |
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7 / 30 page  CYF0018V CYF0036V CYF0072V Document Number: 001-53687 Rev. *J Page 7 of 30 Architecture The CYF0072V, CYF0036V, and CYF0018V are of memory arrays of 72-Mbit, 36-Mbit, and 18-Mbit respectively. The memory organization is user configurable and word sizes can be selected as × 9, × 12, × 16, × 18, × 20, × 24, × 32, or × 36. The logic blocks to implement FIFO functionality and the associated features are built around these memory arrays. The input and output data buses have a maximum width of 36 bits. The input data bus goes to an input register and the data flow from the input register to the memory is controlled by the write logic block. The inputs to the write logic block are WCLK, WEN and IE. When the writes are enabled through WEN and if the inputs are enabled by IE, then the data on the input bus is written into the memory array at the rising edge of WCLK. This also increments the write pointer. Enabling writes but disabling the data input pins through IE only increments the write pointer without doing any writes or altering the contents of the location. Similarly, the output register is connected to the data output bus. Transfer of contents from the memory to the output register is controlled by the read control logic. The inputs to the read control logic include RCLK, REN, OE, RT and MARK. When reads are enabled by REN and outputs are enabled through OE, the data from the memory pointed by the read pointer is transferred to the output data bus at the rising edge of RCLK along with active low DVal. If the outputs are disabled but the reads enabled, the outputs are in high impedance state, but internally the read pointer is incremented. During write operation, the number of writes performed is always a even number (i.e., minimum write burst length is two and number of writes always a multiple of two). Whereas during read operation, the number of reads performed can be even or odd (i.e., minimum read burst length is one). The MARK signal is used to ‘mark’ the location from which data is retransmitted when requested. Reset Logic The FIFO can be reset in two ways: Master Reset (MRS) and Partial Reset (PRS). The MRS initializes the read and write pointers to zero and sets the output register to all zeroes. It also resets the configuration registers to their default values. The word size is configured through pins; values of the three PORTSZ pins are latched during MRS. A Master Reset is required after power-up before accessing the FIFO. The PRS resets only the read and write pointer to the first location and does not affect the programmed configuration registers. Flag Operation This device provides five flag pins to indicate the condition of the FIFO contents. Full Flag The Full Flag (FF) goes LOW when the device is full. Write operations are inhibited whenever FF is LOW regardless of the state of WEN. FF is synchronized to WCLK, that is, it is exclusively updated by each rising edge of WCLK. The worst case assertion latency for Full Flag is four. As the user cannot know that the FIFO is full for four clock cycles, it is possible that user continues writing data during this time. In this case, the four data word written will be stored to prevent data loss and these words have to be read back in order for full flag to get de-asserted.The minimum number of reads required to de-assert full-flag is two and the maximum number of reads required to de-assert full flag is six. Half-Full Flag The Half-Full (HF) flag goes LOW when half of the memory array is written. The assertion of HF is synchronized to WCLK. The assertion and de-assertion of Half-Full flag with associated latencies is explained in Latency Table on page 14. Empty Flag The Empty Flag (EF) goes LOW when the device is empty. Read operations are inhibited whenever EF is LOW, regardless of the state of REN. EF is synchronized to RCLK, that is, it is exclusively updated by each rising edge of RCLK. The assertion and de-assertion of empty flag with associated latencies is explained in Latency Table on page 14. Programmable Almost-Empty and Almost-Full Flags The CYF0072V includes programmable Almost-Empty and Almost-Full flags. Each flag is programmed (see Programming Flag Offsets and Configuration Registers on page 8) a specific distance from the corresponding boundary flags (Empty or Full). (offset can range from 16 to 1024) When the FIFO contains the number of words (or fewer) for which the flags are programmed, the PAF or PAE is asserted, signifying that the FIFO is either almost-full or almost-empty. The PAF flag signal transition is caused by the rising edge of the write clock and the PAE flag transition is caused by the rising edge of the read clock. The assertion and de-assertion of empty flag with associated latencies is explained in Latency Table on page 14. Retransmit from Mark Operation The retransmit feature is useful for transferring packets of data repeatedly. It enables the receipt of data to be acknowledged by the receiver and retransmitted if necessary. The retransmit feature is used when the number of writes after MARK is equal to or less than the depth of the FIFO and at least one word has been read since the last reset cycle. A HIGH pulse on RT resets the internal read pointer to a physical location of the FIFO that is marked by the user (using the MARK pin). With every valid read cycle after retransmit, previously accessed data is read and the read pointer is incremented until it is equal to the write pointer. Flags are governed by the relative locations of the read and write pointers and are updated during a retransmit cycle. Data written to FIFO after activation of RT are also transmitted. The full depth of the FIFO can be repeatedly retransmitted. To mark a location, the Mark pin is asserted when reading that particular location. Flow-through Mailbox Register This feature transfers data from input to output directly by bypassing the FIFO sequence. When MB signal is asserted the data present in D[35:0] will be available at Q[35:0] after two WCLK cycles. Normal read and write operations are not allowed during flow-through mailbox operation. Before starting Flow-through mailbox operation FIFO read should be completed to make data valid DVal high in order to avoid data loss from FIFO. The width of flow-through mailbox register always corresponds to port size. |
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