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CYF0036V33L-133BGXI Datasheet(PDF) 11 Page - Cypress Semiconductor |
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CYF0036V33L-133BGXI Datasheet(HTML) 11 Page - Cypress Semiconductor |
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11 / 30 page  CYF0018V CYF0036V CYF0072V Document Number: 001-53687 Rev. *J Page 11 of 30 Memory Organization for Different Port Sizes The 72-Mbit memory has different organization for different port sizes. Table 5 shows the depth of the FIFO for all port sizes. Note that for all port sizes, four to eight locations are not available for writing the data and are used to safeguard against false synchronization of empty and full flags. Read/Write Clock Requirements The read and write clocks must satisfy the following requirements: ■ Both read (RCLK) and write (WCLK) clocks should be free-running. ■ The clock frequency for both clocks should be between the minimum and maximum range given in Electrical Characteristics on page 13. ■ The WCLK to RCLK ratio should be in the range of 0.5 to 2. For proper FIFO operation, the device must determine which of the input clocks – RCLK or WCLK – is faster. This is evaluated by using counters after the MRS cycle. The device uses two 10-bit counters inside (one running on RCLK and other on WCLK), which count 1,024 cycles of read and write clock after MRS. The clock of the counter which reaches its terminal count first is used as master clock inside the FIFO. When there is change in the relative frequency of RCLK and WCLK during normal operation of FIFO, user can specify it by using “Fast CLK bit” in the configuration register (0xA). “1” - indicates freq (WCLK) > freq (RCLK) “0” - indicates freq (WCLK) < freq (RCLK) The result of counter evaluated frequency is available in this register bit. User can override the counter evaluated frequency for faster clock by changing this bit. Whenever there is a change in this bit value, user must wait tPLL time before issuing the next read or write to FIFO. Figure 3. Using Two CYFX072V for Width Expansion FF FF EF EF WRITE CLOCK (WCLK) WRITE ENABLE (WEN) PAE HF FF CYFX072V CYFX072V 36 72 DATA IN (D) 36 READ CLOCK (RCLK) READ ENABLE (REN) OUTPUT ENABLE(OE) 36 DATA OUT (Q) 36 72 PAF EF Table 5. Word Size Selection PORTSZ[2:0] Word Size FIFO Depth Memory Size 000 × 9 8 Meg 72 Mbit 001 × 12 4 Meg 48 Mbit 010 × 16 4 Meg 64 Mbit 011 × 18 4 Meg 72 Mbit 100 × 20 2 Meg 40 Mbit 101 × 24 2 Meg 48 Mbit 110 × 32 2 Meg 64 Mbit 111 × 36 2 Meg 72 Mbit |
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