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CYRF69213-40LFXC Datasheet(PDF) 5 Page - Cypress Semiconductor |
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CYRF69213-40LFXC Datasheet(HTML) 5 Page - Cypress Semiconductor |
5 / 85 page CYRF69213 Document Number: 001-07552 Rev. *G Page 5 of 85 Pin Configurations Pin Name Function 1 P0.4 Individually configured GPIO 2 Xtal_in 12 MHz Crystal. External clock in 3, 7, 16 VCC Connected to pin 24 via 0.047 F capacitor 4 P0.3 Individually configured GPIO 5 P0.1 Individually configured GPIO 6, 9, 39 Vbat Connected to pin 24 via 0.047 Fshunt capacitor 8 P2.1 GPIO. Port 2 Bit 1 10 RF Bias RF pin voltage reference 11 RFp Differential RF input to/from antenna 12 GND Ground 13 RFn Differential RF to/from antenna 14, 17, 18, 20, 36 NC 15 P2.0 GPIO. Port 2 Bit 0 19 RESV Reserved. Must connect to GND 21 P1.0 / D+ GPIO 1.0 / Low speed USB I/O 22 P1.1 / D– GPIO 1.1 / Low speed USB I/O 23 VDD_micro 4.0–5.5 for 12 MHz CPU/4.75–5.5 for 24 MHz CPU 24 P1.2 / VREG Must be configured as 3.3 V output. It must have a 1–2 F output capacitor 25 P1.3 / nSS Slave select SPI Pin 26 P1.4 / SCK Serial Clock Pin from MCU function to radio function 27 IRQ Interrupt output, configure high/low or GPIO 28 P1.5 / MOSI Master Out Slave In 29 MISO Master In Slave Out, from radio function. Can be configured as GPIO 30 XOUT Bufferd CLK, PACTL_n or GPIO 31 PACTL Control for external PA or GPIO 32 P1.6 GPIO. Port 1 Bit 6 33 VIO I/O interface voltage. Connected to pin 24 via 0.047 F 34 Reset Radio Reset. Connected to VDD via 0.47 F capacitor or to microcontroller GPIO pin. Must have a RESET = HIGH event the very first time power is applied to the radio otherwise the state of the radio function control registers is unknown 35 P1.7 GPIO. Port 1 Bit 7 36 VDD_1.8 Regulated logic bypass. Connected via 0.47 F to GND 37 L/D Connected to GND 38 P0.7 GPIO. Port 0 Bit 7 40 Vreg Connected to pin 24 41 E-pad Must be connected to GND 42 Corner Tabs Do not connect corner tabs |
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