ADS7843

6

SBAS090B

www.ti.com

+V

CC

X+

Y+

X–

Y–

GND

IN3

IN4

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

DCLK

CS

DIN

BUSY

DOUT

PENIRQ

+V

CC

V

REF

Serial/Conversion Clock

Chip Select

Serial Data In

Converter Status

Serial Data Out

+

1

µF

to

10

µF

(Optional)

+2.7V to +5V

ADS7843

Auxiliary Inputs

Touch

Screen

0.1

µF

Pen Interrupt

100k

Ω (optional)

0.1

µF

THEORY OF OPERATION

The ADS7843 is a classic Successive Approximation Regis-

ter (SAR) ADC. The architecture is based on capacitive

redistribution which inherently includes a sample-and-hold

function. The converter is fabricated on a 0.6

µs CMOS

process.

The basic operation of the ADS7843 is shown in Figure 1.

The device requires an external reference and an external

clock. It operates from a single supply of 2.7V to 5.25V. The

The value of the reference voltage directly sets the input

range of the converter. The average reference input current

depends on the conversion rate of the ADS7843.

The analog input to the converter is provided via a four-

channel multiplexer. A unique configuration of low on-resis-

tance switches allows an unselected ADC input channel to

provide power and an accompanying pin to provide ground for

an external device. By maintaining a differential input to the

converter and a differential reference architecture, it is pos-

sible to negate the switch’s on-resistance error (should this be

a source of error for the particular measurement).

ANALOG INPUT

See Figure 2 for a block diagram of the input multiplexer on the

ADS7843, the differential input of the ADC, and the converter’s

differential reference. Table I and Table II show the relation-

the configuration of the ADS7843. The control bits are pro-

vided serially via the DIN pin—see the Digital Interface section

of this data sheet for more details.

When the converter enters the hold mode, the voltage

difference between the +IN and –IN inputs (see Figure 2) is

captured on the internal capacitor array. The input current on

the analog inputs depends on the conversion rate of the

device. During the sample period, the source must charge

the internal sampling capacitor (typically 25pF). After the

capacitor has been fully charged, there is no further input

current. The rate of charge transfer from the analog source

to the converter is a function of conversion rate.

A2

A1

A0

X+

Y+

IN3

IN4

X SWITCHES

Y SWITCHES

0

0

1

+IN

GND

OFF

ON

GND

1

0

1

+IN

GND

ON

OFF

GND

0

1

0

+IN

GND

OFF

OFF

GND

1

1

0

+IN

GND

OFF

OFF

GND

NOTE: (1) Internal node, for clarification only—not directly accessible by the user.

A2

A1

A0

X+

Y+

IN3

IN4

X SWITCHES

Y SWITCHES

00

1

+IN

–Y

OFF

ON

+Y

–Y

10

1

+IN

–XON

OFF

+X

–X

0

1

0

+IN

GND

OFF

OFF

GND

1

1

0

+IN

GND

OFF

OFF

GND

NOTE: (1) Internal node, for clarification only—not directly accessible by the user.

FIGURE 1. Basic Operation of the ADS7843.