ADS7870

SBAS124C − DECEMBER 1999 − REVISED DECEMBER 2005

www.ti.com

5

ELECTRICAL CHARACTERISTICS

For Internal Functions (1), −40

°C ≤ TA ≤ 85°C, VDD = 5 V, BUFIN = 2.5 V (using external reference), 2.5-MHz CCLK and 2.5-MHz SCLK (unless

otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Multiplexer

On resistance

100

Ω

Off resistance

1

G

Ω

Off channel leakage

On channel = 5.2 V,

Off channel = 0 V

VLNx = 5.2 V

100

pA

Off channel leakage

current

On channel = 0 V,

Off channel = 5.2 V

100

pA

On channel leakage

On channel = 5.2 V,

Off channel = 0 V

100

pA

On channel leakage

current

On channel = 0 V,

Off channel = 5.2 V

100

pA

PGA Amplifier

Input capacitance (2)

4 to 9.7

pF

Input impedance (2)

Common mode

6

M

Ω

Input impedance (2)

Differential

7

M

Ω

Offset voltage

100

µV

Small signal bandwidth

5/Gain

MHz

Settling time

G = 1

0.3

µs

Settling time

G = 20

6.4

µs

Analog-To-Digital Converter DC Characteristics

Resolution

12

Bits

Integral linearity error

±0.5

LSB

Differential linearity error

±0.5

LSB

No missing codes

12

Bits

Offset error

REFIN = 2.5 V

±0.5

LSB

Full-scale (gain) error

±0.02

%

Common mode rejection, RTI of A/D

80

dB

Power supply rejection, RTI of ADS7870

External reference, VDD = 5 V ±10%

60

dB

PGA Plus A/D Converter Sampling Dynamics

fCCLK = 2.5 MHz, DF = 1

Throughput rate

48 CCLK cycles

52

kHz

Conversion time

12 CCLK cycles

4.8

µs

Acquisition time

28 CCLK cycles

9.6

µs

Auto zero time

8 CCLK cycles

3.2

µs

Aperture delay

36 CCLK cycles

12.8

µs

Small signal bandwidth

5

MHz

Step response

1 Complete Conversion Cycle

(1) The specifications for the total system are overall analog input to digital output specifications. The specifications for internal functions indicate

the performance of the individual functions in the ADS7870.

(2) The ADS7870 uses switched capacitor techniques for the programmable gain amplifier and A/D converter. A characteristic of such circuits is that

the input capacitance at any selected LNx pin changes during the conversion cycle.