Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.NET

X  

MCM69R818AZP5 Datasheet(PDF) 1 Page - Motorola, Inc

Part # MCM69R818AZP5
Description  4M Late Write HSTL
Download  20 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  MOTOROLA [Motorola, Inc]
Direct Link  http://www.freescale.com
Logo MOTOROLA - Motorola, Inc

MCM69R818AZP5 Datasheet(HTML) 1 Page - Motorola, Inc

  MCM69R818AZP5 Datasheet HTML 1Page - Motorola, Inc MCM69R818AZP5 Datasheet HTML 2Page - Motorola, Inc MCM69R818AZP5 Datasheet HTML 3Page - Motorola, Inc MCM69R818AZP5 Datasheet HTML 4Page - Motorola, Inc MCM69R818AZP5 Datasheet HTML 5Page - Motorola, Inc MCM69R818AZP5 Datasheet HTML 6Page - Motorola, Inc MCM69R818AZP5 Datasheet HTML 7Page - Motorola, Inc MCM69R818AZP5 Datasheet HTML 8Page - Motorola, Inc MCM69R818AZP5 Datasheet HTML 9Page - Motorola, Inc Next Button
Zoom Inzoom in Zoom Outzoom out
 1 / 20 page
background image
MCM69R736A
•MCM69R818A
1
MOTOROLA FAST SRAM
Advance Information
4M Late Write HSTL
The MCM69R736A/818A is a 4 megabit synchronous late write fast static RAM
designed to provide high performance in secondary cache and ATM switch,
Telecom, and other high speed memory applications. The MCM69R818A
organized as 256K words by 18 bits, and the MCM69R736A organized as 128K
words by 36 bits wide are fabricated in Motorola’s high performance silicon gate
BiCMOS technology.
The differential CK clock inputs control the timing of read/write operations of
the RAM. At the rising edge of the CK clock all addresses, write enables, and
synchronous selects are registered. An internal buffer and special logic enable
the memory to accept write data on the rising edge of the CK clock a cycle after
address and control signals. Read data is driven on the rising edge of the CK
clock also.
The RAM uses HSTL inputs and outputs. The adjustable input trip – point (Vref)
and output voltage (VDDQ) gives the system designer greater flexibility in
optimizing system performance.
The synchronous write and byte enables allow writing to individual bytes or the
entire word.
The impedance of the output buffers is programmable allowing the outputs to
match the impedance of the circuit traces which reduces signal reflections.
• Byte Write Control
• Single 3.3 V +10%, – 5% Operation
• HSTL – I/O (JEDEC Standard JESD8–6 Class I Compatible)
• HSTL – User Selectable Input Trip–Point
• HSTL – Compatible Programmable Impedance Output Drivers
• Register to Register Synchronous Operation
• Asynchronous Output Enable
• Boundary Scan (JTAG) IEEE 1149.1 Compatible
• Differential Clock Inputs
• Optional x 18 or x 36 organization
• MCM69R736A/818A–5 = 5 ns
MCM69R736A/818A–6 = 6 ns
MCM69R736A/818A–7 = 7 ns
MCM69R736A/818A–8 = 8 ns
• Sleep Mode Operation (ZZ Pin)
• 119 Bump, 50 mil (1.27 mm) Pitch, 14 mm x 22 mm Plastic Ball Grid Array
(PBGA) Package
This document contains information on a new product. Specifications and information herein are subject to change without notice.
Order this document
by MCM69R736A/D
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MCM69R736A
MCM69R818A
ZP PACKAGE
PBGA
CASE 999–01
REV 1
8/20/97
© Motorola, Inc. 1997


Similar Part No. - MCM69R818AZP5

ManufacturerPart #DatasheetDescription
logo
Motorola, Inc
MCM69R818A MOTOROLA-MCM69R818A Datasheet
57Kb / 7P
   Memory Products
More results

Similar Description - MCM69R818AZP5

ManufacturerPart #DatasheetDescription
logo
Motorola, Inc
MCM69L736A MOTOROLA-MCM69L736A Datasheet
225Kb / 20P
   4M Late Write HSTL
MCM69R736C MOTOROLA-MCM69R736C Datasheet
520Kb / 20P
   4M Late Write HSTL
MCM63R836A MOTOROLA-MCM63R836A Datasheet
385Kb / 21P
   8M Late Write HSTL
MCM69L737A MOTOROLA-MCM69L737A Datasheet
211Kb / 20P
   4M Late Write LVTTL
MCM69R737A MOTOROLA-MCM69R737A Datasheet
212Kb / 20P
   4M Late Write LVTTL
MCM69R738C MOTOROLA-MCM69R738C Datasheet
511Kb / 20P
   4M Late Write 2.5 V I/O
MCM69L738A MOTOROLA-MCM69L738A Datasheet
212Kb / 20P
   4M Late Write 2.5 V I/O
MCM69R738A MOTOROLA-MCM69R738A Datasheet
213Kb / 20P
   4M Late Write 2.5 V I/O
logo
GSI Technology
GS8171DW36AC GSI-GS8171DW36AC Datasheet
1,007Kb / 33P
   18Mb 誇1x1Dp HSTL I/O Double Late Write SigmaRAM
logo
NEC
UPD4443362 NEC-UPD4443362 Datasheet
113Kb / 16P
   4M-BIT CMOS SYNCHRONOUS FAST STATIC RAM 128K-WORD BY 36-BIT HSTL INTERFACE / REGISTER-REGISTER / LATE WRITE
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.NET
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com