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AT24MAC602 Datasheet(PDF) 9 Page - ATMEL Corporation |
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AT24MAC602 Datasheet(HTML) 9 Page - ATMEL Corporation |
9 / 28 page 9 Atmel AT24MAC402/602 [DATASHEET] 8807A–SEEPR–6/12 Figure 4-3. Write Cycle Timing SCL Serial Clock, SDA: Serial Data I/O Note: 1. The write cycle time tWR is the time from a valid Stop condition of a write sequence to the end of the internal clear/write cycle. Figure 4-4. Data Validity Figure 4-5. Start and Stop Condition t WR (1) Stop Condition Start Condition WordN SCL SDA 8th bit ACK SDA SCL Data Stable Data Stable Data Change SDA SCL Start Stop |
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