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AT24CS04-SSUM-T Datasheet(PDF) 8 Page - ATMEL Corporation |
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AT24CS04-SSUM-T Datasheet(HTML) 8 Page - ATMEL Corporation |
8 / 24 page 8 Atmel AT24CS04/08 [PRELIMINARY DATASHEET] 8766B–SEEPR–8/12 Figure 7-2. Bus Timing SCL: Serial Clock, SDA: Serial Data I/O Figure 7-3. Write Cycle Timing SCL: Serial Clock, SDA: Serial Data I/O Note: 1. The write cycle time tWR is the time from a valid Stop condition of a write sequence to the end of the internal clear/write cycle. SCL SDA IN SDA OUT t F t HIGH t LOW t LOW t R t AA t DH t BUF t SU.STO t SU.DAT t HD.DAT t HD.STA t SU.STA t WR (1) Stop Condition Start Condition WORD N SCL SDA 8 th Bit ACK |
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