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Atmel AT24MAC402/602 [DATASHEET]

8807A–SEEPR–6/12

Figure 4-6. Output Acknowledge

5.

Device Addressing

Standard EEPROM Access: The 2K EEPROM requires an 8-bit device address word following a start condition to

enable the chip for a read or write operation (see Table 8-1 on page 16).

The device address word consists of a mandatory one-zero sequence for the first four most-significant bits ‘1010’(Ah)

for normal read and write operations and ‘0110’ (6h) for writing to the Software Write Protect Register.

The next three bits in the protocol sequence are the A2, A1, and A0 device address bits. These three bits must match

The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high,

and a write operation is initiated if this bit is low. Upon a compare of the device address, the EEPROM will output a zero.

If a compare is not made, the device will return to a standby state. The device will not acknowledge if the Write Protect

Register has been programmed and the control code is ‘0110’(6h).

Serial Number Access: The AT24MAC402/602 incorporates an extended memory block containing a

factory-programmed 128-bit serial number. Access to this memory location is obtained by beginning the device address

word with a ‘1011’(Bh) sequence. The behavior of the next three bits (A2, A1, and A0) remain the same as during a

standard memory addressing sequence.

The eighth bit of the device address needs to be set to a one to read the serial number. A zero in this bit position, other

than during a dummy write sequence to set the address pointer, will result in a unknown condition and behavior. Writing

or altering the 128-bit serial number is not possible as it is permanently write protected. Further specific protocol is

needed to address the serial number feature of the part. For more details on accessing this special feature, See “Read

Operations” on page 15.

EUI Address Access: The AT24MAC402/602 utilizes an extended memory block containing a factory-programmed

read-only EUI-48 or EUI-64 address respectively. Access to this memory block is obtained by beginning the device

address word with a ‘1011’ (Bh) sequence. The behavior of the next three bits (A2, A1, and A0) remain the same as

during a standard memory addressing sequence.

The eighth bit of the device address needs to be set to a one to read the EUI address. A zero in this bit position, other

than during a dummy write sequence to set the address pointer, will result in a unknown condition and behavior.

Attempting to write or alter the EUI address is not possible as it is permanently write protected. Further specific protocol

is needed to address this feature of the part. For more details on accessing this special feature, see “Read Operations”

on page 15.

SCL

Data IN

Data OUT

Start

Acknowledge

18

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