SL74HC299N datasheet(4/8 Pages) SLS

Part #	SL74HC299N

Description	8-Bit Bidirectional Universal Shift Register with Parallel I/O

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Manufacturer	SLS [System Logic Semiconductor]

Direct Link	http://www.slsemicon.co.kr/e_index.htm

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SL74HC299

System Logic

Semiconductor

SLS

AC ELECTRICAL CHARACTERISTICS(C

L=50pF,Input t r=tf=6.0 ns)

VCC

Guaranteed Limit

Symbol

Parameter

V

25

°C to

-55

°C

≤85°C

≤125°C

Unit

fmax

Maximum Clock Frequency (50% Duty Cycle)

(Figures 1 and 5)

2.0

4.5

6.0

5.0

25

29

4.0

20

24

3.4

17

20

MHz

tPLH, tPHL

Maximum Propagation Delay, Clock to QA’ or QH’

(Figures 1 and 5)

2.0

4.5

6.0

170

34

29

215

43

37

255

51

43

ns

tPLH, tPHL

Maximum Propagation Delay, Clock to QA thru QH

(Figures 1 and 5)

2.0

4.5

6.0

160

32

27

200

40

34

240

48

41

ns

tPHL

Maximum Propagation Delay, Reset to QA’ or QH’

(Figures 2 and 5)

2.0

4.5

6.0

175

35

30

220

44

37

265

53

45

ns

tPHL

Maximum Propagation Delay, Reset to QA thru QH

(Figures 2 and 5)

2.0

4.5

6.0

190

38

32

240

48

41

285

57

48

ns

tPLZ, tPHZ

Maximum Propagation Delay , OE1, OE2, S1, or S2

to QA thru QH (Figures 3 and 6)

2.0

4.5

6.0

150

30

26

190

38

33

225

45

38

ns

tPZL, tPZH

Maximum Propagation Delay , OE1, OE2, S1, or S2

to QA thru QH (Figures 3 and 6)

2.0

4.5

6.0

150

30

26

190

38

33

225

45

38

ns

tTLH, tTHL

Maximum Output Transition Time, QA thru QH

(Figures 1 and 5)

2.0

4.5

6.0

60

12

10

75

15

13

90

18

15

ns

tTLH, tTHL

Maximum Output Transition Time, QA’ thru QH’

(Figures 1 and 5)

2.0

4.5

6.0

75

15

13

95

19

16

110

22

19

ns

CIN

Maximum Input Capacitance)

-

10

pF

COUT

Maximum Three-State I/O Capacitance

(I/O in High-Impedance State), QA thru QH

-

15

pF

Power Dissipation Capacitance (Per Package),

Output Enable

Typical @25

°C,V

CC=5.0 V

CPD

Used to determine the no-load dynamic power

consumption:

PD=CPDVCC

2f+I

CCVCC

240

pF

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