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74SSTUB32865A

SLAS562 – NOVEMBER 2007

FUNCTION TABLE (continued)

INPUTS

OUTPUTS

Dn,

QODT,

RESET

DCS0

DCS1

CSGateEN

CK

CK

DODTn,

Qn

QCS0

QCS1

QCKE

DCKEn

H

H

H

L

L or H

L or H

X

H

H

H

H

↑

↓

L

H

H

L

H

H

H

H

↑

↓

H

H

H

H

H

H

H

H

L or H

L or H

X

L

X or floating X or floating X or floating

X or floating

X or floating

X or floating

L

L

L

L

PARITY AND STANDBY FUNCTION

INPUTS

OUTPUT

RESET

CK

CK

DCS0

DCS1

Σ OF INPUTS = H

D1–D22

H

↑

↓

L

X

Even

L

H

H

↑

↓

L

X

Odd

L

L

H

↑

↓

L

X

Even

H

L

H

↑

↓

L

X

Odd

H

H

H

↑

↓

X

L

Even

L

H

H

↑

↓

X

L

Odd

L

L

H

↑

X

L

Even

H

L

H

↑

↓

X

L

Odd

H

H

H

↑

↓

H

H

X

X

(3)

H

L or H

L or H

X

X

X

X

L

X or floating

X or floating

X or floating

X or floating

X

X or floating

(1)

PARIN arrives one clock cycle after the data to which it applies.

(2)

This transition assumes that PTYERR is high at the crossing of CK going high and CK going low. If PTYERR goes low, it stays latched

low for a minimum of two clock cycles or until RESET is driven low. If two or more consecutive errors occur, the PTYERR output is

driven low and latched low for a clock duration equal to the parity error duration or until RESET is driven low. For PTYERR computation

CSGateEN is a don't care.

(3)

If DCS0, DCS1 and CSGateEN are driven high, the device is placed in a low-power mode (LPM). If a parity error occurs on the clock

cycle before the device enters the LPM and the PTYERR output is driven low, it stays latched low for the LPM duration plus two clock

cycles or until RESET is driven low.

10

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