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ADS1282HPW Datasheet(PDF) 11 Page - Texas Instruments |
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ADS1282HPW Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 60 page  ADS1282-HT www.ti.com SBAS446F – DECEMBER 2009 – REVISED AUGUST 2011 ELECTRICAL CHARACTERISTICS (PW PACKAGE) (continued) Limit specifications at –55°C to 175°C. Typical specifications at 25°C, AVDD = 2.5 V, AVSS = –2.5 V, fCLK (1) = 4.096 MHz, VREFP = 2.5 V, VREFN = –2.5 V, DVDD = 3.3 V, CAPN – CAPP = 10 nF, PGA = 1, High-Resolution Mode, and fDATA = 1000 SPS, unless otherwise noted. TA = –55°C to 125°C TA = 175°C (2) PARAMETER CONDITIONS UNIT MIN TYP MAX MIN TYP MAX High-resolution mode –1.5 –1.0 –0.5 –1.5 –1 –0.5 % Gain error(9) Low-power mode –1 –0.5 0 –1 –0.5 0 % Gain error after calibration(8) 0.0002 0.0002 % PGA = 1 2 2 ppm/ °C Gain drift PGA = 16 9 11 ppm/ °C Gain matching(10) 0.3 0.8 0.4 0.8 % Common-mode rejection fCM = 60Hz (11) 82 110 82 114 dB AVDD, 80 90 84 AVSS Power-supply rejection fPS = 60Hz (11) dB DVDD 90 115 106 VOLTAGE REFERENCE INPUTS (AVDD – (AVDD – (VREF = VREFP – Reference input voltage 0.5 5 AVSS) + 0.5 AVSS) + V VREFN) 0.2 0.2 AVSS – VREFP – AVSS – VREFP – V Negative reference input VREFN 0.1 0.5 0.1 0.5 VREFN + AVDD + 0.1 VREFN + V Positive reference input VREFP AVDD + 0.1 0.5 0.5 High-resolution mode 85 85 k Ω Reference input impedance Low-power mode 170 170 k Ω DIGITAL FILTER RESPONSE Passband ripple ±0.003 ±0.003 dB 0.375 × fDATA 0.375 × Hz Passband ( –0.01 dB) fDATA 0.413 × fDATA 0.413 × Hz Bandwidth ( –3 dB) fDATA High-pass filter corner 0.1 10 0.1 10 Hz Stop band attenuation(12) 135 135 dB 0.500 × fDATA 0.500 × Hz Stop band fDATA Minimum phase filter(13) 5/fDATA 5/fDATA Group delay s Linear phase filter 31/fDATA 31/fDATA Minimum phase filter 62/fDATA 62/fDATA Settling time (latency) s Linear phase filter 62/fDATA 62/fDATA DIGITAL INPUT/OUTPUT 0.8 × DVDD 0.8 X V VIH DVDD DVDD DVDD VIL DGND 0.2 × DVDD DGND 0.2 × DVDD V IOH = 1mA 0.8 × 0.8 X V VOH DVDD DVDD VOL IOL = 1mA 0.2 × DVDD 0.2 × DVDD V Input leakage 0 < VDIGITAL IN < DVDD ±10 ±10 μA Clock input fCLK 1 4.096 1 4.096 MHz Serial clock rate fSCLK fCLK/2 fCLK/2 MHz (9) The PGA output impedance and the modulator input impedance results in –1% systematic gain error (high-resolution mode) and –0.5% error (low-power mode). (10) Gain match relative to PGA = 1. (11) fCM is the input common-mode frequency. fPS is the power-supply frequency. (12) Input frequencies in the range of NfCLK/512 ± fDATA/2 (N = 1, 2, 3...) can mix with the modulator chopping clock. In these frequency ranges intermodulation = 120 dB, typ. (13) At dc. See Figure 49. Copyright © 2009–2011, Texas Instruments Incorporated 11 |
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