bq24278

SLUSB04 – JUNE 2012

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PIN FUNCTIONS

PIN

NAME

NUMBER

I/O

DESCRIPTION

YFF

RGE

Input power supply. IN is connected to the external DC supply (AC adapter or alternate power

IN

A1-A4

21

I

source). Bypass IN to PGND with at least a 1

μF ceramic capacitor.

AGND

A5-A7

22

I

Ground terminal. Connect to the thermal pad (for QFN only) and the ground plane of the circuit.

Reverse Blocking MOSFET and High Side MOSFET Connection Point for High Power Input.

Bypass PMID to PGND with at least a 4.7

μF ceramic capacitor. Use caution when connecting

PMID

B1-B4

20

O

an external load to PMID. The PMID output is not current limited. Any short on PMID will result

in damage to the IC.

BYP

B5-B7

23

O

Bypass for internal supply. Bypass BYP to GND with at least a 0.1µF ceramic capacitor.

SW

C1–C7

18

O

Inductor Connection. Connect to the switched side of the external inductor.

Ground terminal for Switching FET. Connect to the thermal pad (for QFN only) and the ground

PGND

D1–D7

16, 17

—

plane of the circuit.

IN Input Current Limit Programming Input. Connect a resistor from ILIM to GND to program the

ILIM

E1

15

I

input current limit for IN. The current limit is programmable from 1A to 2.5A.

IC Hardware Disable Input. Drive CD high to place the bq24278 in high-z mode. Drive CD low

CD

E2

2

I

for normal operation.

Input DPM Programming Input. Connect a resistor divider from IN to PGND with VDPM

connected to the center tap to program the Input Voltage based Dynamic Power Management

VDPM

E3

1

I

See the Input Voltage based Dynamic Power Management section for a detailed explanation.

Charge Enable Input. CE is used to disable or enable the charge process. A low logic level (0)

enables charging and a high logic level (1) disables charging. When charging is disabled, the

CE

E4

24

I

SYS output remains in regulation, but BAT is disconnected from SYS. Supplement mode is still

available if the system load demands cannot be met by the supply.

DRV_S

E5, E6

3, 4

I

Supply for Internal Circuits. Connect DRV_S to DRV directly.

High Side MOSFET Gate Driver Supply. Connect a 0.01

μF ceramic capacitor (voltage rating >

BOOT

E7

19

I

10V) from BOOT to SW to supply the gate drive for the high side MOSFETs.

System Voltage Sense and Charger FET Connection. Connect SYS to the system output at the

SYS

F1–F4

13,14

I/O

output bulk capacitors. Bypass SYS locally with 1

μF.

External Discharge MOSFET Gate Connection. BGATE drives an external P-Channel MOSFET

BGATE

F5

10

O

to provide a very low resistance discharge path. Connect BGATE to the gate of the external

MOSFET. BGATE is low during supplement mode and when no input is connected.

Power Good Open Drain Output. /PG is pulled low when a valid supply is connected to IN. A

PG

F6

7

I

this range, PG is high impedance.

Gate Drive Supply. DRV is the bias supply for the gate drive of the internal MOSFETs. bypass

DRV to PGND with a 1

μF ceramic capacitor. DRV may be used to drive external loads up to

DRV

F7

6

O

Battery Connection. Connect to the positive terminal of the battery. Additionally, bypass BAT to

BAT

G1–G4

11, 12

I/O

GND with a 1

μF capacitor.

Battery Pack NTC Monitor. Connect TS to the center tap of a resistor divider from DRV to

GND. The NTC is connected from TS to GND. The TS function in the bq24278 provides 2

TS

G5

9

I

thresholds for Hot/ Cold shutoff, with 2 additional thresholds for JEITA compliance. See the

NTC Monitor section for more details on operation and selecting the resistor values.

Charge Status Open Drain Output. CHG is pulled low when a charge cycle starts and remains

CHG

G6

8

O

low while charging. CHG is high impedance when the charging terminates and when no supply

exists. CHG does not indicate recharge cycles.

Charge Current Programming Input. Connect a resistor from ISET to GND to program the fast

ISET

G7

5

I

charge current. The charge current is programmable from 550mA to 2.5A.

There is an internal electrical connection between the exposed thermal pad and the VSS pin of

Thermal

the device. The thermal pad must be connected to the same potential as the VSS pin on the

—

Pad

—

Pad

printed circuit board. Do not use the thermal pad as the primary ground input for the device.

VSS pin must be connected to ground at all times.

8

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