BUF20800-Q1

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SBOS571

– AUGUST 2011

The BUF20800-Q1 will acknowledge each data byte. If the master terminates communication early by sending a

STOP or START condition on the bus, the specified register will not be updated. Updating the DAC register is not

the same as updating the DAC output voltage. See the Output Latch section.

The process of updating multiple DAC registers begins the same as when updating a single register. However,

instead of sending a STOP condition after writing the addressed register, the master continues to send data for

the next register. The BUF20800-Q1 automatically and sequentially steps through subsequent registers as

additional data is sent. The process continues until all desired registers have been updated or a STOP condition

is sent.

To write to multiple DAC registers:

1. 1. Send a START condition on the bus.

2. Send the device address and read/write bit = LOW. The BUF20800-Q1 will acknowledge this byte.

3. Send either the DAC_1 address byte to start at the first DAC, or send the address byte for whichever DAC

will be the first in the sequence of DACs to be updated. The BUF20800-Q1 will begin with this DAC and step

through subsequent DACs in sequential order.

4. Send the bytes of data; begin by sending the most significant byte (bits D15

−D8, of which only bits D9 and

D8 have meaning), followed by the least significant byte (bits D7

−D0). The first two bytes are for the DAC

addressed in step 3 above. Its register is automatically updated after receiving the second byte. The next two

bytes are for the following DAC. That DAC register is updated after receiving the fourth byte. This process

continues until the registers of all following DACs have been updated.

5. Send a STOP condition on the bus.

The BUF20800-Q1 will acknowledge each byte. To terminate communication, send a STOP or START condition

on the bus. Only DAC registers that have received both bytes of data will be updated.

Reading

Reading a DAC register will return the data stored in the DAC. This data can differ from the data stored in the

DAC register. See the Output Latch section.

To read the DAC value:

1. Send a START condition on the bus.

2. Send the device address and read/write bit = LOW. The BUF20800-Q1 will acknowledge this byte.

3. Send the DAC address byte. Bits D7

−D5 must be set to 0; Bits D4−D0 are the DAC address. Only DAC

addresses 00000 to 10011 are valid and will be acknowledged.

4. Send a START or STOP/START condition on the bus.

5. Send correct device address and read/write bit = HIGH. The BUF20800-Q1 will acknowledge this byte.

6. Receive two bytes of data. They are for the specified DAC. The first received byte is the most significant byte

(bits D15

−D8; only bits D9 and D8 have meaning); the next byte is the least significant byte (bits D7−D0).

7. Acknowledge after receiving the first byte.

8. Do not acknowledge the second byte to end the read transaction.

Communication may be terminated by sending a premature STOP or START condition on the bus, or by not

sending the acknowledge.

Copyright

© 2011, Texas Instruments Incorporated

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