CC1110F32RSP datasheet(5/247 Pages) TI1

Part #	CC1110F32RSP

Description	Low-Power SoC (System-on-Chip) with MCU, Memory, Sub-1 GHz RF Transceiver, and USB Controller

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Manufacturer	TI1 [Texas Instruments]

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5 / 247 page

CC1110Fx / CC1111Fx

SWRS033G

Page 5 of 244

1

Register Conventions

Each SFR is described in a separate table. The table heading is given in the following format:

REGISTER NAME (SFR Address) - Register Description.

Each RF register is described in a separate table. The table heading is given in the following format:

XDATA Address: REGISTER NAME - Register Description

All register descriptions include a symbol denoted R/W describing the accessibility of each bit in the

register. The register values are always given in binary notation unless prefixed by ‘0x’, which

indicates hexadecimal notation.

Symbol

Access Mode

R/W

Read/write

R

Read only

R0

Read as 0

R1

Read as 1

W

Write only

W0

Write as 0

W1

Write as 1

H0

Hardware clear

H1

Hardware set

Table 1: Register Bit Conventions

2

Key Features (in more details)

2.1

High-Performance

and

Low-Power

8051-Compatible Microcontroller

 Optimized 8051 core which typically

gives 8x the performance of a standard

8051

 Two data pointers

 In-circuit

interactive

debugging

is

supported

by

the

IAR

Embedded

Workbench through a simple two-wire

serial interface

 SW compatible with CC2510Fx/CC2511Fx

2.2

8/16/32

KB

Non-volatile

Program

Memory and 1/2/4 kB Data Memory

 8, 16, or 32 KB of non-volatile flash

memory,

in-system

programmable

through a simple two-wire interface or

by the 8051 core

 Minimum flash memory endurance:

1000 write/erase cycles

 Programmable read and write lock of

portions of flash memory for software

security

 1, 2, or 4 kB of internal SRAM

2.3

Full-Speed USB Controller (

CC1111Fx )

 5 bi-directional endpoints in addition to

control endpoint 0

 Full-Speed, 12 Mbps transfer rate

 Support

for

Bulk,

Interrupt,

and

Isochronous endpoints

 1024 bytes of dedicated endpoint FIFO

memory

 8 - 512 byte data packet size supported

 Configurable FIFO size for IN and OUT

direction of endpoint

2.4

I

2S Interface

 Industry standard I2S interface for

transfer of digital audio data

 Full duplex

 Mono and stereo support

 Configurable sample rate and sample

size

 Support for -law compression and

expansion

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