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CDC421A106RGET Datasheet(PDF) 4 Page - Texas Instruments |
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CDC421A106RGET Datasheet(HTML) 4 Page - Texas Instruments |
4 / 15 page DEVICE INFORMATION CE NC NC NC NC NC NC V CC V CC NC NC NC 1 2 3 4 5 6 18 17 16 15 14 13 ThermalPad (BottomSide) CDC421AXXX CDC421AXXX SCAS875 – MAY 2009 ....................................................................................................................................................................................................... www.ti.com RGE PACKAGE QFN-24 (TOP VIEW) CDC421Axxx Pin Descriptions TERMINAL ESD NAME NO. TYPE PROTECTION DESCRIPTION VCC 16, 17 Power Y 3.3-V power supply GND 8, 9 Ground Y Ground XIN1 21 I Y In crystal input mode, connect XIN1 to one end of the crystal and XIN2 to the other end of the crystal. In LVCMOS single-ended driven mode, XIN1 (pin 21) acts as input reference XIN2 22 I N and XIN2 should connect to GND. Chip enable (LVCMOS input) CE 1 I Y CE = 1 enables the device and the outputs. CE = 0 disables all current sources (LVPECLP = LVPECLN = Hi-Z). High-speed positive differential LVPECL output. (Outputs are enabled by CE OUTP 10 O Y pin.) High-speed negative differential LVPECL output. (Outputs are enabled by CE OUTN 7 O Y pin.) 2–6, 11–15, TI test pin. Do not connect; leave floating. NC — Y 18–20, 23, 24 4 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated |
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