16-Bit Registered Transceiver

CY74FCT163652

SCCS052 - March 1997 - Revised March 2000

Data sheet acquired from Cypress Semiconductor Corporation.

Data sheet modified to remove devices not offered.

Copyright

Features

• Low power, pin-compatible replacement for LCX and

LPT families

• 5V tolerant inputs and outputs

• 24 mA balanced drive outputs

• Power-off disable outputs permits live insertion

• Edge-rate control circuitry for reduced noise

• FCT-C speed at 4.6 ns

• Latch-up performance exceeds JEDEC standard no. 17

• ESD > 2000V per MIL-STD-883D, Method 3015

• Typical output skew < 250 ps

• Industrial temperature range of –40˚C to +85˚C

• TSSOP (19.6-mil pitch) or SSOP (25-mil pitch)

Std 883D

Functional Description

The CY74FCT163652 is a 16-bit, high-speed, low-power,

registered transceiver that is organized as two independent

8-bit bus transceivers with three-state D-type registers and

control circuitry arranged for multiplexed transmission of data

directly from the input bus or from the internal storage

registers. OEAB and OEBA control pins are provided to control

the transceiver functions. SAB and SBA control pins are

provided to select either real-time or stored data transfer.

Data on the A or B data bus, or both, can be stored in the

internal D flip-flops by LOW-to-HIGH transitions at the

appropriate clock pins (CLKAB or CLKBA), regardless of the

select or enable control pins. When SAB and SBA are in the

real-time transfer mode, it is also possible to store data without

using the internal D-type flip-flops by simultaneously enabling

OEAB and OEBA. In this configuration, each output reinforces

its input. Thus, when all other data sources to the two sets of

bus lines are at high impedance, each set of bus lines will

remain at its last state.

The CY74FCT163652 has 24-mA balanced output drivers

with current limiting resistors in the outputs. This reduces the

need for external terminating resistors and provides for

minimal undershoot and reduced ground bounce. The inputs

and outputs were designed to be capable of being driven by

5.0V buses, allowing them to be used in mixed voltage

systems as translators. The outputs are also designed with a

power-off disable feature enabling them to be used in

applications requiring live insertion.

TO 7 OTHER CHANNELS

C

D

B REG

C

D

A REG

C

D

B REG

C

D

A REG

TO 7 OTHER CHANNELS

Logic Block Diagrams