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XDAC34SH84IZAY Datasheet(PDF) 6 Page - Texas Instruments |
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XDAC34SH84IZAY Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 77 page  DAC34SH84 SLAS808B – FEBRUARY 2012 – REVISED JULY 2012 www.ti.com PIN FUNCTIONS (continued) PIN I/O DESCRIPTION NAME NO. LVDS SYNC positive input. Internal 100- Ω termination resistor. If unused it can be left unconnected. SYNCP A8 I The PARITY, SYNC, and ISTR inputs are rotated to allow complete reversal of the data interface when setting the rev_interface bit in register config1. SYNCN B8 I LVDS SYNC negative input RESETB N10 I Active-low input for chip RESET. Internal pullup Transmit enable active-high input. Internal pulldown To enable analog output data transmission, set sif_txenable in register config3 to 1 or pull the CMOS TXENA N9 I TXENA pin to high. To disable analog output, set sif_txenable to 0 and pull the CMOS TXENA pin to low. The DAC output is forced to midscale. TESTMODE L11 I This pin is used for factory testing. Internal pulldown. Leave unconnected for normal operation Digital supply voltage. This supply pin is also used for factory fuse programming. Connect to VFUSE D7, L7 I DACVDD or DIGVDD for normal operation ORDERING INFORMATION(1) TA ORDER CODE PACKAGE DRAWING/TYPE TRANSPORT MEDIA QUANTITY DAC34SH84IZAY Tray 160 –40°C to 85°C ZAY / 196 NFBGA DAC34SH84IZAYR Tape and reel 1000 (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the device product folder at www.ti.com. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VALUE UNIT MIN MAX DACVDD, DIGVDD, CLKVDD –0.5 1.5 V VFUSE –0.5 1.5 V Supply voltage range(2) IOVDD, IOVDD2 –0.5 4 V AVDD, PLLAVDD –0.5 4 V DAB[15..0]P/N, DCD[15..0]P/N, DATACLKP/N, ISTRP/N, PARITYCDP/N, –0.5 IOVDD + 0.5 V SYNCP/N DACCLKP/N, OSTRP/N –0.5 CLKVDD + 0.5 V ALARM, SDO, SDIO, SCLK, SDENB, SLEEP, RESETB, TESTMODE, –0.5 IOVDD2 + 0.5 V Pin voltage range(2) TXENA IOUTAP/N, IOUTBP/N, IOUTCP/N, IOUTDP/N –1.0 AVDD + 0.5 V EXTIO, BIASJ –0.5 AVDD + 0.5 V LPF –0.5 PLLAVDD + 0.5 V Peak input current (any input) 20 mA Peak total input current (all inputs) –30 mA Absolute maximum junction temperature, TJ 150 °C Storage temperature range, Tstg –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) Measured with respect to GND 6 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): DAC34SH84 |
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