DLPC300

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DLPS023A – JANUARY 2012 – REVISED JULY 2012

Figure 5 illustrates the bit planes and corresponding output triggers for 3-bit, 6-bit, and 12-bit RBG. Table 1

shows the allowed pattern combinations in relation to the bit depth of the pattern.

Figure 5. Bit Planes and Output Trigger for 3-, 6-, and 12-Bit RGB Input

Table 1. Allowed Pattern Combinations

NUMBER OF

FRAME

External Video Sequence

IMAGES

PATTERN RATE

RATE

PER FRAME

1 bit per pixel

24

24 × Frame Rate

15, 30, 40, or

60 Hz

2 bits per pixel

12

12 × Frame Rate

3 bits per pixel

15, 30, 45, or

8

8 × Frame Rate

60 Hz

4 bits per pixel

15, 30, 40, or

6

6 × Frame Rate

60 Hz

Monochrome

5 bits per pixel

4

4 × Frame Rate

15, 30, 45, or

60 Hz

6 bits per pixel

4

4 × Frame Rate

7 bits per pixel

15, 30, 40, or

3

3 × Frame Rate

60 Hz

8 bits per pixel

2

2 × Frame Rate

1-bit per color pixel

8

8 × Frame Rate

(3-bit per pixel)

2-bit per color pixel

4

4 × Frame Rate

(6-bit per pixel)

4-bit per color pixel

2

15, 30, 45, or

2 × Frame Rate

(12-bit per pixel)

60 Hz

RGB

5/6/5-bit RGB pixel

(16-bit per pixel)

6-bit per color pixel

1

Frame Rate

(18-bit per pixel)

8-bit per color pixel

(24-bit per pixel)

An optional FPGA (see the DLPR300 Software Folder) can be added to the system to manage the bit-planes

stored in the mDDR. The mDDR accomodates four 608 × 684 images of 24-bit RGB data or 96 bit-planes (24 bit-

planes × 4 images). By pre-loading the mDDR with these bit-planes, faster frame rates can be achieved. The 96

bit-plane buffer is arranged in a circular buffer style, meaning that the last bit-plane addition to the buffer replaces

the oldest stored bit-plane. Figure 6 shows the overall system with the optional FPGA.

Copyright © 2012, Texas Instruments Incorporated

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