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DRV8801-Q1 Datasheet(PDF) 6 Page - Texas Instruments |
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DRV8801-Q1 Datasheet(HTML) 6 Page - Texas Instruments |
6 / 23 page Charge Pump nFAULT PHASE GND nSLEEP ENABLE OUT SENSE VCP GND CP2 CP1 OUT VBB VBB 3.3K .22 uf .1 uf .1 uf 100 uf .1 uf VREG MODE Low-Side Gate Supply Control Logic Motor lead Protection Bias Supply PAD VDD 3.3K VBB OUT+ OUT- SENSE UVLO STB STG TSD Optional + - DRV8800-Q1 DRV8801-Q1 SLVSAS7 – FEBRUARY 2011 www.ti.com DRV8800-Q1 FUNCTIONAL BLOCK DIAGRAM 6 Submit Documentation Feedback © 2011, Texas Instruments Incorporated Product Folder Link(s): DRV8800-Q1 DRV8801-Q1 |
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