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INA129SKGD1 Datasheet(PDF) 4 Page - Texas Instruments

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Part # INA129SKGD1
Description  PRECISION, LOW POWER INSTRUMENTATION AMPLIFIERS
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

INA129SKGD1 Datasheet(HTML) 4 Page - Texas Instruments

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INA128-HT, INA129-HT
SBOS501D – JANUARY 2010 – REVISED JUNE 2012
www.ti.com
ABSOLUTE MAXIMUM RATINGS
(1)
over operating free-air temperature range (unless otherwise noted)
VALUE
UNIT
VS
Supply voltage
±18
V
Analog input voltage range
±40
V
Output short-circuit (to ground)
Continuous
HKJ, HKQ, KGD and JD
–55 to 210
packages
TA
Operating temperature
°C
D package
–55 to 175
HKJ, HKQ, KGD and JD
–55 to 210
packages
TSTG
Storage temperature range
°C
D package
–55 to 175
Lead temperature (soldering, 10s)
300
°C
(1)
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
THERMAL CHARACTERISTICS FOR D PACKAGE
INA128
THERMAL METRIC(1)
D
UNITS
8 PINS
θJA
Junction-to-ambient thermal resistance(2)
110
θJCtop
Junction-to-case (top) thermal resistance(3)
57
θJB
Junction-to-board thermal resistance(4)
54
°C/W
ψJT
Junction-to-top characterization parameter(5)
11
ψJB
Junction-to-board characterization parameter(6)
53
θJCbot
Junction-to-case (bottom) thermal resistance(7)
N/A
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2)
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3)
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4)
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5)
The junction-to-top characterization parameter,
ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining
θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6)
The junction-to-board characterization parameter,
ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining
θJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7)
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
XXX
THERMAL CHARACTERISTICS FOR JD PACKAGE
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
High-K board(2), no airflow
64.9
Junction-to-ambient thermal
θJA
°C/W
resistance(1)
No airflow
83.4
θJB
Junction-to-board thermal resistance High-K board without underfill
27.9
°C/W
θJC
Junction-to-case thermal resistance
6.49
°C/W
(1)
The intent of
θJA specification is solely for a thermal performance comparison of one package to another in a standardized environment.
This methodology is not meant to and will not predict the performance of a package in an application-specific environment.
(2)
JED51-7, high effective thermal conductivity test board for leaded surface mount packages
4
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Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): INA128-HT INA129-HT


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