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SN75C091A Datasheet(PDF) 4 Page - Texas Instruments |
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SN75C091A Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 106 page  2–1 2 Architecture 2.1 Block Diagram The functional block architecture of the SN75C091A is as shown in Figure 2–1 below: Handler Interrupt FIFO Receive FIFO Transmit Control ARB/SEL Controller REQ/ACK SCSI File Register Interface Processor Micro– Interface DMA Parity GEN/CHK Byte Stack Control Command Sequencer Parity GEN/CHK Parity GEN/CHK Handshake Figure 2–1. SN75C091A Functional Block Architecture 2.1.1 Command Sequencer The heart of the SN75C091A is a large state machine called the command sequencer. Microprocessor commands to the SN75C091A are interpreted by the command sequencer, which then activates subordinate state machines (e.g. the arbitration controller, REQ/ACK handshake controller, and DMA interface controller) to perform the functions necessary to carry out each command. The command sequencer enables the SN75C091A to execute powerful multiphase SCSI sequences with very few interrupts. 2.1.2 SCSI REQ/ACK Handshake Controller The REQ/ACK handshake controller handles requests from the command sequencer to perform single SCSI phase transfers such as Message, Command, Status, and Data. REQ, ACK, ATN, MSG, C/D and I/O are controlled and/or monitored (depending on the mode, target or initiator) to transfer information between the transmit and receive FIFOs and the SCSI bus. The REQ/ACK handshake controller supports both synchronous and asynchronous data transfers. |
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Similar Description - SN75C091A |
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