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MSP430F2370TRHAR Datasheet(PDF) 10 Page - Texas Instruments |
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MSP430F2370TRHAR Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 67 page  MSP430F23x0 SLAS518E – AUGUST 2006 – REVISED AUGUST 2011 www.ti.com Interrupt Vector Addresses The interrupt vectors and the power-up starting address are located in the address range of 0xFFFF to 0xFFC0. The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence. If the reset vector (located at address 0xFFFE) contains 0xFFFF (for example, if flash is not programmed), the CPU goes into LPM4 immediately after power up. Table 6. Interrupt Vector Addresses SYSTEM INTERRUPT SOURCE INTERRUPT FLAG WORD ADDRESS PRIORITY INTERRUPT Power-up PORIFG External Reset RSTIFG Watchdog WDTIFG Reset 0xFFFE 31, highest Flash key violation KEYV PC out of range(1) (2) NMI NMIIFG (non) –maskable Oscillator Fault OFIFG (non) –maskable 0xFFFC 30 Flash memory access violation ACCVIFG(2)(3) (non) –maskable Timer_B3 TBCCR0 CCIFG(4) maskable 0xFFFA 29 TBCCR1 and TBCCR2, Timer_B3 maskable 0xFFF8 28 CCIFGs, TBIFG(2)(4) Comparator_A+ CAIFG maskable 0xFFF6 27 Watchdog timer WDTIFG maskable 0xFFF4 26 Timer_A3 TACCR0 CCIFG(4) maskable 0xFFF2 25 TACCR1 CCIFG, Timer_A3 TACCR2 CCIFG, maskable 0xFFF0 24 TAIFG(2)(4) USCI_A0/USCI_B0 Receive UCA0RXIFG, maskable 0xFFEE 23 USCI_B0 I2C Status UCB0RXIFG(2)(5) USCI_A0/USCI_B0 Transmit UCA0TXIFG, maskable 0xFFEC 22 USCI_B0 I2C Receive/Transmit UCB0TXIFG(2)(6) 0xFFEA 21 0xFFE8 20 I/O port P2 (eight flags) P2IFG.0 to P2IFG.7(2)(3) maskable 0xFFE6 19 I/O port P1 (eight flags) P1IFG.0 to P1IFG.7(2)(3) maskable 0xFFE4 18 0xFFE2 17 0xFFE0 16 See (7) 0xFFDE 15 See (8) 0xFFDC to 0xFFC0 14 to 0, lowest (1) A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0x0000 to 0x01FF) or from within unused address range. (2) Multiple source flags (3) (non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot. Nonmaskable: neither the individual nor the general interrupt-enable bit will disable an interrupt event. (4) Interrupt flags are located in the module. (5) In SPI mode: UCB0RXIFG. In I2C mode: UCALIFG, UCNACKIFG, ICSTTIFG, UCSTPIFG (6) In UART/SPI mode: UCB0TXIFG. In I2C mode: UCB0RXIFG, UCB0TXIFG (7) This location is used as bootstrap loader security key (BSLSKEY). A 0xAA55 at this location disables the BSL completely. A zero (0x0) disables the erasure of the flash if an invalid password is supplied. (8) The interrupt vectors at addresses 0xFFDC to 0xFFC0 are not used in this device and can be used for regular program code if necessary. 10 Copyright © 2006–2011, Texas Instruments Incorporated |
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