TFP410-EP

PanelBus

™ DIGITAL TRANSMITTER

SGLS344A − JULY 2006 − REVISED MAY 2011

4

POST OFFICE BOX 655303

Terminal Functions (Continued)

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

DE

2

I

Data enable. As defined in DVI 1.0 specification, the DE signal allows the transmitter to encode pixel

data or control data on any given input clock cycle. During active video (DE = high), the transmitter

encodes pixel data, DATA[23:0]. During the blanking interval (DE = low), the transmitter encodes

HSYNC, VSYNC, and CTL[3:1].

HSYNC

4

I

Horizontal sync input

IDCK−

IDCK+

56

57

I

Differential clock input. The TFP410 supports both single-ended and fully differential clock input

modes. In the single-ended clock input mode, the IDCK+ input (pin 57) should be connected to the

single-ended clock source and the IDCK− input (pin 56) should be tied to GND. In the differential clock

input mode, the TFP410 uses the crossover point between the IDCK+ and IDCK− signals as the timing

reference for latching incoming data DATA[23:0], DE, HSYNC, and VSYNC. The differential clock input

mode is only available in the low signal swing mode.

VSYNC

5

I

Vertical sync input

Configuration/Programming

BSEL/SCL

15

I

enabled or disabled. This pin is only 3.3-V tolerant.

selects 12-bit input, dual-edge input mode.

descriptions section). In this configuration, this pin has an open-drain output that requires an external

DKEN

35

I

disabled. When deskew is enabled, the input clock to data setup/hold time can be adjusted in discrete

pins DK[3:1] (see the data deskew section). A low level disables deskew and the default trim setting is

used.

DSEL/SDA

14

I/O

This pin is only 3.3-V tolerant.

differential input clock mode (see the universal graphics controller interface modes section).

configuration, this pin has an open-drain output that requires an external 5-kΩ pullup resistor

EDGE/HTPLG

9

I

disabled. This input is 3.3-V tolerant only.

the input clock IDCK+. A low level selects the primary latch to occur on the falling edge of the input clock

IDCK+. This is the case for both single-ended and differential input clock modes.

VESA™ P&D and DFP standards). When used for hot-plug detection, this pin requires a series 1-KΩ

resistor.

ISEL/RST

13

I

register descriptions section.

changed to their default values and are not preserved from before the reset.