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THS8083CPZP Datasheet(PDF) 7 Page - Texas Instruments |
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THS8083CPZP Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 61 page  1–1 1 Introduction The THS8083 is a solution for digitizing video and graphic signals in RGB or YUV/YCbCr color spaces. The device supports pixel rates up to 80 MHz. Therefore, it can be used for PC graphics digitizing up to the VESA standard of XGA (1024 X 768) resolution at 75 Hz screen refresh rate, and in video environments for the digitizing of digital TV formats, including HDTV. The THS8083 is powered from a single 3.3-V supply and integrates a triple high-performance A/D converter with clamping functions and variable gain, independently programmable for each channel. Separate clamping ranges are provided for RGB and YUV operation modes of the device. The clamp timing window is provided by an external pulse or can be generated internally. The programmable gain amplifiers consist of coarse and fine gain control blocks. The THS8083 includes slicing circuitry on the Y or G input to support sync-on-green or sync-on-luminance extraction. The THS8083 further contains a completely digital PLL block, consisting of phase-frequency detector (PFD), discrete time oscillator (DTO) and programmable divider to generate the (sampling) clock from the incoming horizontal sync (HS) signal, depending on the incoming video resolution. Any pixel rate can be generated in the 10-80 MHz range. Moreover, the output phase of the synthesized clock can be controlled with sub-pixel accuracy (31 uniform settings). Programmable time constants allow the PLL loop bandwidth to be changed by the integrated PLL loop filter. Alternatively, the user may bypass the PLL when an external pixel clock is available. Even then the DTO synthesized clock is still available externally and can therefore be used in other parts of the (graphics) system. Extensive PLL and input monitoring functions are integrated for typical functionality required in LCD/DMD monitor/projection systems (input format detection, autocalibration). All programming of the part is done via an industry-standard normal/fast I2C interface, which supports both reading and writing of register settings. The THS8083 is available in a space-saving TQFP 100-pin PowerPAD package. 1.1 Features The THS8083 supports the following features: • Analog Channels – Three digitizing channels, each with independently controllable clamp, PGA, and ADC. – Clamp: 256-step programmable RGB or YUV clamping during external or internal clamp timing window – PGA: 6-bit coarse/5-bit fine programmable gain amplifier – ADC: 8 bit 80 MSPS A/D converter – Composite sync: Integrated sync-on-green/sync-on-luminance extraction – Support for ac-coupled input signals • PLL – Fully integrated digital PLL (including loop filter) for pixel clock generation – 10-80 MHz pixel clock generation from reference input – Adjustable PLL loop bandwidth for minimum jitter or fast acquisition/wide capture range modes – 5-bit programmable subpixel accuracy positioning of sampling phase – Noise gates on HS input to avoid false PLL updating PowerPAD is a trademark of Texas Instruments. |
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