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TI380C25PGE Datasheet(PDF) 8 Page - Texas Instruments |
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TI380C25PGE Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 71 page  TI380C25 TOKEN-RING COMMPROCESSOR SPWS012 – JANUARY 1995 8 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 Pin Functions (Continued) PIN I/O† DESCRIPTION NAME NO. I/O† DESCRIPTION MW 142 O Local-memory write. MW is used to specify a write cycle on the local-memory bus. The data on the MADH0 – MADH7 and MADL0 – MADL7 buses is valid while MW is low. DRAMs latch data on the falling edge of MW, while SRAMs latch data on the rising edge of MW. H = Not a local-memory write cycle L = Local-memory write cycle NMI 33 I Nonmaskable interrupt request. NMI must be left unconnected. OSCIN 135 I External oscillator input. OSCIN provides the clock frequency to the TI380C25 for a 4-MHz or 6-MHz internal bus (see Notes 5 and 6). CLKDIV OSCIN H 64 MHz for a 4-MHz local bus L 32 MHz for a 4-MHz local bus or 48 MHz for a 6-MHz local bus OSCOUT 122 O Oscillator output CLKDIV OSCOUT L OSCIN / 4 (if OSCIN = 32 MHz, OSCOUT = 8 MHz; if OSCIN = 48 MHz, OSCOUT = 12 MHz) H OSCIN / 8 (if OSCIN = 64 MHz, OSCOUT = 8 MHz) PRTYEN 41 I Parity enable. The value on PRTYEN is loaded into the PEN bit of the SIFACL register at reset (i.e., when SRESET is asserted or the ARESET bit in the SIFACL register is set) to form a default value. PRTYEN enables parity checking for the local memory. H = Local-memory data bus checked for parity (see Note 1). L = Local-memory data bus not checked for parity. NSELOUT0 NSELOUT1 40 119 O O Network selection outputs. NSELOUT0 and NSELOUT1 are controlled by the host through the corresponding bits of the SIFACL register. The value of these bits / signals can be changed only while the TI380C25 is reset. NSELOUT0 NSELOUT1 DESCRIPTION L H 16-Mbps token ring H H 4-Mbps token ring SADH0 SADH1 SADH2 SADH3 SADH4 SADH5 SADH6 SADH7 97 96 95 94 93 92 86 85 I/O System address / data bus — high byte (see Note 1).These lines make up the most significant byte of each address word (32-bit address bus) and data word (16-bit data bus). The most significant bit is SADH0, and the least significant bit is SADH7. Address multiplexing: Bits 31 – 24 and bits 15 – 8 Data multiplexing: Bits 15 – 8 SADL0 SADL1 SADL2 SADL3 SADL4 SADL5 SADL6 SADL7 76 75 74 70 69 68 67 66 I/O System address / data bus — low byte (see Note 1). These lines make up the least significant byte of each address word (32-bit address bus) and data word (16-bit data bus). The most significant bit is SADL0 and the least significant bit is SADL7. Address multiplexing: Bits 23 – 16 and bits 7 – 0 Data multiplexing : Bits 7 – 0 † I = input, O = output NOTES: 1. Pin has an internal pullup device to maintain a high-voltage level when left unconnected (no etch). 5. Pin has an expanded input voltage specification. 6. A maximum of two TI380C25 devices can be connected to any one oscillator. |
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