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FSD156MRBN Datasheet(PDF) 9 Page - Fairchild Semiconductor |
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FSD156MRBN Datasheet(HTML) 9 Page - Fairchild Semiconductor |
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9 / 16 page  © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FSD156MRBN • Rev. 1.0.0 9 Functional Description 1. Startup: At startup, an internal high-voltage current source supplies the internal bias and charges the external capacitor (CVcc) connected to the VCC pin, as illustrated in Figure 17. When VCC reaches 12V, the FSD156MRBN begins switching and the internal high- voltage current source is disabled. Normal switching operation continues and the power is supplied from the auxiliary transformer winding unless VCC goes below the stop voltage of 7.5V. Figure 17. Startup Block 2. Soft-Start: The internal soft-start circuit increases PWM comparator inverting input voltage, together with the SenseFET current, slowly after startup. The typical soft-start time is 15ms. The pulse width to the power switching device is progressively increased to establish the correct working conditions for the transformers, inductors, and capacitors. The voltage on the output capacitors is progressively increased to smoothly establish the required output voltage. This helps prevent transformer saturation and reduces stress on the secondary diode during startup. 3. Feedback Control: This device employs Current- Mode control, as shown in Figure 18. An opto-coupler (such as the FOD817) and shunt regulator (such as the KA431) are typically used to implement the feedback network. Comparing the feedback voltage with the voltage across the RSENSE resistor makes it possible to control the switching duty cycle. When the reference pin voltage of the shunt regulator exceeds the internal reference voltage of 2.5V, the opto-coupler LED current increases, pulling down the feedback voltage and reducing drain current. This typically occurs when the input voltage is increased or the output load is decreased. 3.1 Pulse-by-Pulse Current Limit: Because Current- Mode control is employed, the peak current through the SenseFET is limited by the inverting input of PWM comparator (VFB*), as shown in Figure 18. Assuming that the 90μA current source flows only through the internal resistor (3R + R =25kΩ), the cathode voltage of diode D2 is about 2.8V. Since D1 is blocked when the feedback voltage (VFB) exceeds 2.8V, the maximum voltage of the cathode of D2 is clamped at this voltage. Therefore, the peak value of the current through the SenseFET is limited. 3.2 Leading-Edge Blanking (LEB): At the instant the internal SenseFET is turned on, a high-current spike usually occurs through the SenseFET, caused by primary-side capacitance and secondary-side rectifier reverse recovery. Excessive voltage across the RSENSE resistor leads to incorrect feedback operation in the Current-Mode PWM control. To counter this effect, the leading-edge blanking (LEB) circuit inhibits the PWM comparator for tLEB (300ns) after the SenseFET is turned on. Figure 18. Pulse Width Modulation Circuit |
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