SN65LVPE501

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SLLSE30A – MAY 2010 – REVISED MAY 2012

Table 1. Pin Description

PIN

NUMBER

NAME

I/O TYPE

DESCRIPTION

HIGH SPEED DIFFERENTIAL I/O PINS

8

RX1+

I, CML

9

RX1–

I, CML

Non-inverting and inverting CML differential input for CH 1 and CH 2. These pins are tied to an

internal voltage bias by dual termination resistor circuit.

20

RX2+

I, CML

19

RX2–

I, CML

23

TX1+

O, CML

22

TX1–

O, CML

Non-inverting and inverting CML differential output for CH 1 and CH 2. These pins are

internally tied to voltage bias by termination resistors.

11

TX2+

O, CML

12

TX2–

O, CML

5

EN_RXD

I, LVCMOS

Sets device operation modes per Table 2. Internally pulled to VCC

14

PS

I, LVCMOS

Select auto-low power save mode per Table 2. Internally pulled to GND

7

RST

I, LVCMOS

Reset device, input active Low. Internally pulled to VCC

24

RSVD

I, LVCMOS

Reserved for factory test. Must be connected to GND

3,16

DE1, DE2

I, LVCMOS

2,17

EQ1, EQ2

I, LVCMOS

4, 15

OS1, OS2

I, LVCMOS

POWER PINS

1,13

VCC

Power

Positive supply should be 3.3V ± 10%

6,10,18,21

GND

Power

Supply ground

(1)

(2)

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