Lattice Semiconductor Corporation

(1.31, 30-MAR-2012)

www.latticesemi.com/

8

RAM4K Block

Table 10 provides timing information for the logic in a RAM4K block, which includes the paths shown in Figure 9.

Figure 9: RAM4K Timing Circuit

PAD

PIO

PAD

PIO

GBIN

GBUF

WDATA

WCLK

RDATA

RCLK

RAM4K

RAM Block

(256x16)

GBIN

GBUF

Table 10: Typical RAM4K Block Timing

Nominal VCC

1.2 V

Description

Typ.

Write Setup/Hold Time

PIO

input

GBIN

input

Minimum write data setup time on PIO inputs before active clock

edge on GBIN input, include interconnect delay.

0.44

ns

GBIN

input

PIO

input

Minimum write data hold time on PIO inputs after active clock edge

on GBIN input, including interconnect delay.

0

ns

Read Clock-Output-Time

RCLK

clock

input

PIO

output

Clock-to-output delay from RCLK input pin, through RAM4K RDATA

output flip-flop to PIO output pad, including interconnect delay.

4.1

ns

GBIN

input

RCLK

clock

input

Global Buffer Input (GBIN) delay, though Global Buffer (GBUF)

clock network to the RCLK clock input.

1.4

ns

Write and Read Clock Characteristics

WCLK

RCLK

WCLK

RCLK

Write clock High time

0.30

ns

Write clock Low time

0.35

ns

Write clock cycle time

0.71

ns

Sustained write clock frequency

256

MHz