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SM320VC5409GGU10EP Datasheet(PDF) 9 Page - Texas Instruments |
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SM320VC5409GGU10EP Datasheet(HTML) 9 Page - Texas Instruments |
9 / 78 page SM320VC5409EP FIXEDPOINT DIGITAL SIGNAL PROCESSOR SGUS046 − JULY 2003 9 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Terminal Functions (Continued) TERMINAL NAME DESCRIPTION I/O† INTERNAL TERMINAL NAME DESCRIPTION I/O† PIN STATE HOST-PORT INTERFACE SIGNALS (CONTINUED) HR/W Pullup resistor I Read/write. HR/W controls the direction of an HPI transfer. R/W has an internal pullup resistor that is only enabled when HPIENA = 0. HRDY O/Z Ready. The ready output informs the host when the HPI is ready for the next transfer. HRDY goes into the high-impedance state when OFF is low. HINT O/Z Interrupt. This output is used to interrupt the host. When the DSP is in reset, HINT is driven high . The signal goes into the high-impedance state when OFF is low. HPIENA Pulldown resistor I HPI module select. HPIENA must be driven high during reset to enable the HPI. An internal pulldown resistor is always active and the HPIENA pin is sampled on the rising edge of RS. If HPIENA is left open or is driven low during reset, the HPI module is disabled. Once the HPI is disabled, the HPIENA pin has no effect until the ’5409 is reset. HPI16 Pulldown resistor I HPI 16-bit select pin (internal pulldown, default HPI8). HPI16 = 1 selects the non-multiplexed mode. The non-multiplexed mode allows hosts with separate address/data buses to access the HPI address range via the 16 address pins (A15–A0). 16-bit data is also accessible through pins D0 through D15. Host-to-DSP and DSP-to-Host interrupts are not supported. There are no HPIC and HPIA register accesses in the non-multiplexed mode. The HPI16 pin is sampled at RESET. The user should never change the value of the HPI16 pin while the RESET signal is HIGH. SUPPLY PINS CVDD S +VDD. Dedicated 1.8-V power supply for the core CPU DVDD S +VDD. Dedicated 3.3-V power supply for the I/O pins VSS S Ground TEST PINS TCK Schmitt trigger/pullup resistor I IEEE standard 1149.1 test clock. TCK is normally a free-running clock signal with a 50% duty cycle. The changes on the test access port (TAP) of input signals TMS and TDI are clocked into the TAP controller, instruction register, or selected test data register on the rising edge of TCK. Changes at the TAP output signal (TDO) occur on the falling edge of TCK. TDI Pullup resistor I IEEE standard 1149.1 test data input pin with internal pullup device. TDI is clocked into the selected register (instruction or data) on a rising edge of TCK. TDO O/Z IEEE standard 1149.1 test data output. The contents of the selected register (instruction or data) are shifted out of TDO on the falling edge of TCK. TDO is in the high-impedance state except when the scanning of data is in progress. TDO also goes into the high-impedance state when OFF is low. TMS Pullup resistor I IEEE standard 1149.1 test mode select. Pin with internal pullup device. This serial control input is clocked into the TAP controller on the rising edge of TCK. TRST Pulldown resistor I IEEE standard 1149.1 test reset. TRST, when high, gives the IEEE standard 1149.1 scan system control of the operations of the device. If TRST is not connected or is driven low, the device operates in its functional mode, and the IEEE standard 1149.1 signals are ignored. Pin with internal pulldown device. † I = Input, O = Output, Z = High-impedance, S = Supply |
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