12-Bit, 300ksps ADCs with Differential

Track/Hold, and Internal Reference

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5

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Externally clocked conversion

208

SCLK Clock Period

Data I/O

100

ns

SCLK Pulse-Width High

40

ns

SCLK Pulse-Width Low

40

ns

SCLK Fall to DOUT Transition

40

ns

CS Rise to DOUT Disable

40

ns

CS Fall to DOUT Enable

40

ns

DIN to SCLK Rise Setup

40

ns

SCLK Rise to DIN Hold

0

ns

CS Low to SCLK Setup

40

ns

CS High to SCLK Setup

40

ns

CS High After SCLK Hold

0

ns

CS Low After SCLK Hold

0

4

µs

CKSEL = 00

40

ns

CNVST Pulse-Width Low

CKSEL = 01

1.4

µs

Voltage conversion

7

CS or CNVST Rise to EOC

Low (Note 11)

Reference power-up

65

µs

TIMING CHARACTERISTICS (Figure 1)

Note 11: This time is defined as the number of clock cycles needed for conversion multiplied by the clock period. If the internal

reference needs to be powered up, the total time is additive. The internal reference is always used for temperature

measurements.

Typical Operating Characteristics

INTEGRAL NONLINEARITY

vs. OUTPUT CODE

OUTPUT CODE (DECIMAL)

3072

2048

1024

-0.8

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8

1.0

-1.0

04096

MAX11634/MAX11636

INTEGRAL NONLINEARITY

vs. OUTPUT CODE

OUTPUT CODE (DECIMAL)

3072

2048

1024

-0.8

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8

1.0

-1.0

04096

MAX11635/MAX11637

DIFFERENTIAL NONLINEARITY

vs. OUTPUT CODE

OUTPUT CODE (DECIMAL)

3072

2048

1024

-0.8

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8

1.0

-1.0

0

4096

MAX11634/MAX11636