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TMS320TCI100GLZA7 Datasheet(PDF) 2 Page - Texas Instruments |
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TMS320TCI100GLZA7 Datasheet(HTML) 2 Page - Texas Instruments |
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2 / 137 page  TMS320TCI100 FIXEDPOINT DIGITAL SIGNAL PROCESSOR SPRS218I − MAY 2003 − REVISED APRIL 2009 2 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Table of Contents reset 74 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . absolute maximum ratings over operating case temperature range 75 . . . . . . . . . . . . . . . . . . . . . . . . . . recommended operating conditions 75 . . . . . . . . . . . . . . . . electrical characteristics over recommended ranges of supply voltage and operating case temperature 76 . recommended clock and control signal transition behavior 76 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . parameter measurement information 77 . . . . . . . . . . . . . . . input and output clocks 79 . . . . . . . . . . . . . . . . . . . . . . . . . . . asynchronous memory timing 83 . . . . . . . . . . . . . . . . . . . . . programmable synchronous interface timing 87 . . . . . . . . synchronous DRAM timing 92 . . . . . . . . . . . . . . . . . . . . . . . . HOLD/HOLDA timing 102 . . . . . . . . . . . . . . . . . . . . . . . . . . . BUSREQ timing 103 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . reset timing 104 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . external interrupt timing 106 . . . . . . . . . . . . . . . . . . . . . . . . . host-port interface (HPI) timing 107 . . . . . . . . . . . . . . . . . . . peripheral component interconnect (PCI) timing 112 . . . . . multichannel buffered serial port (McBSP) timing 115 . . . . UTOPIA slave timing 126 . . . . . . . . . . . . . . . . . . . . . . . . . . . . timer timing 129 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . general-purpose input/output (GPIO) port timing 130 . . . . JTAG test-port timing 131 . . . . . . . . . . . . . . . . . . . . . . . . . . . mechanical data 132 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . revision history 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GLZ, ZLZ and CLZ BGA packages (bottom view) 4 . . . . . . . . description 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . device characteristics 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . functional block and CPU (DSP core) diagram 7 . . . . . . . . . . . CPU (DSP core) description 8 . . . . . . . . . . . . . . . . . . . . . . . . . . memory map summary 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . peripheral register descriptions 14 . . . . . . . . . . . . . . . . . . . . . . . EDMA channel synchronization events 27 . . . . . . . . . . . . . . . . interrupt sources and interrupt selector 29 . . . . . . . . . . . . . . . . signal groups description 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . device configurations 36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . multiplexed pins 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . debugging considerations 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . terminal functions 41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . development support 61 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . device support 62 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . clock PLL 65 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . general-purpose input/output (GPIO) 68 . . . . . . . . . . . . . . . . . . power-down mode logic 69 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . power-supply sequencing 71 . . . . . . . . . . . . . . . . . . . . . . . . . . . . power-supply decoupling 72 . . . . . . . . . . . . . . . . . . . . . . . . . . . . IEEE 1149.1 JTAG compatibility statement 72 . . . . . . . . . . . . . EMIF device speed 73 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bootmode 74 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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