SN65HVDA1040A-Q1

SLLS995C

– FEBRUARY 2010 – REVISED FEBRUARY 2011

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THERMAL CHARACTERISTICS

TEST CONDITIONS

MIN

TYP

MAX

UNIT

THERMAL METRIC - SOIC

'D' PACKAGE

12.1-D

140

Junction-to-air thermal

12.2-D

112

Junction-to-board thermal

12.3-D

50

Junction-to-case (top) thermal

12.4-D

56

°C/W

Junction-to-case (bottom)

12.5-D

NA

Junction-to-top

12.6-D

13

Junction-to-board

12.7-D

55

THERMAL METRIC - VSON

'DSJ' PACKAGE

12.1-DSJ

290

Junction-to-air thermal

12.2-DSJ

52

Junction-to-board thermal

12.3-DSJ

14

Junction-to-case (top) thermal

12.4-DSJ

56

°C/W

Junction-to-case (bottom)

12.5-DSJ

4.5

Junction-to-top

12.6-DSJ

6

Junction-to-board

12.7-DSJ

19

AVERAGE POWER DISSIPATION AND THERMAL SHUTDOWN

12.5

Input to TXD at 500 kHz, 50% duty cycle

112

Average power dissipation

mW

0 V,

12.6

170

Input to TXD at 500 kHz, 50% duty cycle

Thermal shutdown

12.7

185

°C

temperature

(1)

For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2)

and High-K values are given as reference points to standardized reference boards.

(3)

The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, Low-K board, as

specified in JESD51-3, in an environment described in JESD51-2a.

(4)

The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(5)

The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(6)

The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific

JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(7)

The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(8)

The junction-to-top characterization parameter,

from the simulation data for obtaining

(9)

The junction-to-board characterization parameter,

from the simulation data for obtaining

10

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