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DESERIALIZER SWITCHING CHARACTERISTICS

SN65LV1023A-EP

SN65LV1224B-EP

SGLS358 – SEPTEMBER 2006

over recommended operating supply and temperature ranges (unless otherwise specified)

PARAMETER

TEST

PIN/FREQ

MIN

TYP

MAX

UNIT

CONDITIONS

Receiver out clock period

RCLK

15.15

100

ns

Figure 13

CMOS/TTL low-to-high

ROUT0–ROUT9

1.2

transition time

,

15 pF, See

ns

LOCK, RCLK

CMOS/TTL high-to-low

1.1

Figure 7

transition time

Deserializer delay, See

Room temperature, 10 MHz

1.75

×t

(RCP)

1.75

×t

(RCP)

ns

Figure 14

3.3 V

+4.2

+12.6

66 MHz

1.75

×t

(RCP)

1.75

×t

(RCP)

ns

+7.4

+9.7

RCLK 10 MHz

0.4

×t

(RCP)

0.5

×t

(RCP)

RCLK 66 MHz

0.4

×t

(RCP)

0.5

×t

(RCP)

See Figure 15

ns

10 MHz

–0.4

×t

(RCP)

–0.5

×t

(RCP)

66 MHz

–0.4

×t

(RCP)

–0.5

×t

(RCP)

RCLK duty cycle

40%

50%

60%

ns

High-to-high impedance state

6.5

ns

delay

Low-to-high impedance state

4.7

ns

delay

See Figure 16

High-impedance state to high

5.3

ns

delay

High-impedance state to low

4.7

ns

delay

Deserializer PLL lock time from

10 MHz

850

× t

RFCP

PWRDN (with SYNCPAT)

66 MHz

850

× t

RFCP

µs

See Figure 17,

10 MHz

2

Figure 18,

Deserializer PLL lock time from

66 MHz

0.303

SYNCPAT

High-impedance state to high

LOCK

3

ns

delay (power up)

10 MHz

3680

See Figure 19 and

Deserializer noise margin

ps

(3)

66 MHz

540

(1)

The deserializer delay time for all frequencies does not exceed two serial bit times.

(2)

when the input (RI

±) conditions change from not receiving data to receiving synchronization patterns (SYNCPATs). In order to specify

(3)

11

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