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FUNCTIONAL DESCRIPTION

SYNCHRONIZATION-PATTERN GENERATION (SN65LV1023A)

SN65LV1023A-EP

SN65LV1224B-EP

SGLS358 – SEPTEMBER 2006

The SN65LV1023A and SN65LV1224B are a 10-bit serializer/deserializer chipset designed to transmit data over

differential backplanes or unshielded twisted pair (UTP) at clock speeds from 10 MHz to 66 MHz. The chipset

has five states of operation: initialization mode, synchronization mode, data transmission mode, power-down

mode, and high-impedance mode. The following sections describe each state of operation.

The synchronization-pattern generation is designed to work, as follows:

After SYNC1 or SYNC2 is held high for at least 6T (T = 1 refclk cycle), the SYNC pattern is generated on the

serial line for 1026T. During this 1026-cycle SYNC pattern transmission, it is not required that SYNC1 or SYNC2

be held high.

There are two different cases in which this SYNC pattern generation might be used:

1. SYNC1 or SYNC2 is held high once at least 6T, but no more than 1026T:

In this case, the sync-pattern generation should generate 1026T of SYNC pattern only once, and the data

that follows the SYNC pattern on the serial line should reflect the parallel inputs. In this scenario, the sync

pattern generation is working as it is designed.

2. SYNC1 or SYNC2 is held high continuously at least 1038T (6T to invoke the first series of SYNC pattern,

and 1026T, which is the duration of the first series of the SYNC pattern, and 6T to invoke the second series

of the SYNC pattern):

If the sync-pattern generator operates as it is intended, the user should be able to observe the continuous

SYNC pattern on the serial line. For example, if the SYNC1 or SYNC2 is held high for 1039T, a user can

see the SYNC pattern being generated continuously for 2052T (=1026T+1026T). However, as shown in

Figure 1, the device behaves in a way that, if the SYNC1 or SYNC2 is held high for more than 1038T, it

sends out 1028T of SYNC pattern, plus 4T of data (which reflects the data that is present on the parallel

input at that time) and another 1026T of SYNC pattern. Figure 1 basically shows how the data on the serial

line would be affected if the SYNC1 or SYNC2 is held for an extended period of time.

Figure 1. Sync-Pattern Generation

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