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TMX5702134APGEQQ1 Datasheet(PDF) 1 Page - Texas Instruments |
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TMX5702134APGEQQ1 Datasheet(HTML) 1 Page - Texas Instruments |
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1 / 155 page  TMS570LS3134 TMS570LS2134 TMS570LS2124 www.ti.com SPNS165 – SEPTEMBER 2011 TMS570LSxxx4 16/32-Bit RISC Flash Microcontroller Check for Samples: TMS570LS3134 1 TMS570LSxxx4 16/32-Bit RISC Flash Microcontroller 1.1 Features 1 • High-Performance Microcontroller for Safety • Multiple Communication Interfaces Critical Applications – 10/100 Mbps Ethernet MAC (EMAC) – Dual CPU’s running in lockstep • IEEE 802.3 compliant (3.3V-I/O only) – ECC on flash and RAM interfaces • Supports MII and MDIO – Built-In Self Test for CPU and on-chip RAMs – Three CAN Controllers (DCAN) – Error Signaling Module with Error Pin • 64 mailboxes with parity protection each – Voltage and Clock Monitoring • Compliant to CAN protocol version 2.0B • ARM® Cortex™ – R4F 32-bit RISC CPU – Inter-Integrated Circuit (I2C) – Efficient 1.6DMIPS/MHz with 8-stage pipeline – Three Multi-buffered Serial Peripheral – Floating-Point Unit with Single/Double Interfaces (MibSPI) Precision • 128 Words with Parity Protection each – 12-Region Memory Protection Unit – Two Standard Serial Peripheral Interfaces – Open Architecture with 3rd Party Support (SPI) • Operating Conditions – Local Interconnect Network Interface (LIN) Controller – Up to 180MHz System Clock • Compliant to LIN protocol version 2.1 – Core Supply Voltage (VCC): 1.2V nominal – Standard Serial Communication Interface – I/O Supply Voltage (VCCIO): 3.3V nominal (SCI) • Integrated Memory • Two High-End Timer Modules (N2HET) – Up to 3MB Program Flash with ECC – N2HET1: 32 programmable channels – Up to 256KB RAM with ECC – N2HET2: 20 programmable channels – 64KB Flash for emulated EEPROM – 160 Word Instruction RAM with parity • 16- bit External Memory Interface protection each • Common Platform Architecture – Each includes Hardware Angle Generator – Consistent memory map across family – Dedicated Transfer Unit for each N2HET – Real-Time Interrupt Timer (RTI) OS Timer (HTU) – 96-channel Vectored Interrupt Module (VIM) • Two 10/12-bit Multi-Buffered ADC Modules – 2-channel Cyclic Redundancy Checker (CRC) – ADC1: 24 channels • Direct Memory Access (DMA) Controller – ADC2: 16 channels – 16 Channels and 32 Control Packets – 16 shared channels – Parity protection for control packet RAM – 64 result buffers with parity protection each – DMA Accesses Protected by Dedicated MPU • Packages • Frequency-Modulated Phase-Locked-Loop – 144-pin Quad Flatpack (PGE) [Green] (FMPLL) with Built-In Slip Detector – 337-Ball Grid Array (ZWT) [Green] • Separate Non-Modulating PLL • IEEE 1149.1 JTAG, Boundary Scan and ARM CoreSight Components • JTAG Security Module • Trace and Calibration Capabilities – Embedded Trace Macrocell (ETM-R4) – Data Modification Module (DMM) – RAM Trace Port (RTP) – Parameter Overlay Module (POM) 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCT PREVIEW information concerns products in the formative Copyright © 2011, Texas Instruments Incorporated or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. |
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