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TPS27081ADDCR Datasheet(PDF) 6 Page - Texas Instruments |
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TPS27081ADDCR Datasheet(HTML) 6 Page - Texas Instruments |
6 / 14 page ( ) J(MAX) A (MAX) JA T T PD - = q TPS27081A SLVSBE9A – APRIL 2012 – REVISED JULY 2012 www.ti.com Table 1. Component Values for VOUT Rise Time (continued) Rise Time (sec) VIN (V) R2 ( Ω) C1 (µF) CL (µF)(1) 1.00m 5.0 61.9k 0.01 10.0µ 12.0m 5.0 61.9k 0.12 470µ 21.0m 1.5 61.9k 0.12 470µ 600m 3.0 333k 1.00 10.0µ Low Voltage ON/OFF Interface The VGSQ2 is set by the ON/OFF logic level. To turn ON, the transistor Q2 requires a VGS > 1.0V (Typical). For reliable operation apply ON/OFF logic that has the following VIH and VIL limits: VIHON > 1.0V + IQ2 × R2 V VIHOFF 0.4 V Minimizing IQ2 x R2 drop helps achieve a direct interface with a low voltage ON/OFF logic. To minimize IQ2 x R2 voltage drop select a high R1/R2 ratio. E.g. When VIN= 1.8V, selecting R1/R2 = 40 will require VIH > 1.0 + 45mV and thus allowing a 1.2V GPIO interface. In applications where ON/OFF signal is not available connect ON/OFF pin to VIN. The TPS27081A will turn ON/OFF in sync with the input supply connected to VIN. Note: Connect a pull down resistor between ON/OFF pin to GND when ON/OFF is driven by a high-impedance (tri-state) driver. On-Chip Power Dissipation Use the below equation to calculate TPS27081A on-chip power dissipation PD: PD = IDQ12 × RDSQ1(ON) +IDQ2 2 × RDS Q2(ON) Where, IDQ1 and IDQ2 are the DC current flowing through the transistors Q1 and Q2 respectively. Refer to the ELECTRICAL CHARACTTERISTICS table and/or Figure x to estimate RDSQ1(ON) and RDSQ1(ON) for various values of VGSQ1 and VGSQ2 respectively. Note: MOS switches can get extremely hot when operated in saturation region. As a general guideline, to avoid transistors Q1 and Q2 going into saturation region set VGS > VT +VDS. E.g. VGS > 1.5V and VDS < 200mV ensures switching region. Thermal Reliability For higher reliability it is recommended to limit TPS27081A IC’s die junction temperature to less than 125°C. The IC junction temperature is directly proportional to the on-chip power dissipation. Use the following equation to calculate maximum on-chip power dissipation to achieve the maximum die junction temperature target: Where: TJ(MAX) is the target maximum junction temperature. TA is the operating ambient temperature. R θJA is the package junction to ambient thermal resistance. (4) Improving Package Thermal Performance The package θJA value under standard conditions on a High-K board is listed in the DISSIPATION RATINGS. θJA value depends on the PC board layout. An external heat sink and/or a cooling mechanism, like a cold air fan, can help reduce θJA and thus improve device thermal capabilities. Refer to TI’s design support web page at www.ti.com/thermal for a general guidance on improving device thermal performance. 6 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS27081A |
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