3

Exposed

Thermal Pad

9

10

11

12

8

7

6

5

4

2

1

16

15

14

13

PVIN

PVIN

AVIN

SS/TR

SW

SW

SW

PG

TPS62140

TPS62141, TPS62142, TPS62143

SLVSAJ0

– NOVEMBER 2011

www.ti.com

DEVICE INFORMATION

RGT PACKAGE

(TOP VIEW)

Terminal Functions

I/O

DESCRIPTION

NAME

NO.

SW

1, 2 ,3

O

Switch node, which is connected to the internal MOSFET switches. Connect inductor between SW and

output capacitor.

PG

4

O

Output power-good (High = VOUT ready, Low = VOUT below nominal regulation); open-drain (requires

pullup resistor; goes high-impedance when device is switched off)

FB

5

I

Voltage feedback of adjustable version. Connect resistive voltage divider to this pin. Its recommended to

connect FB to AGND on fixed output-voltage versions for improved thermal performance.

AGND

6

–

Analog ground

FSW

7

I

Switching frequency select (Low

DEF

8

I

Soft-start / tracking pin. An external capacitor connected to this pin sets the internal voltage-reference rise

SS/TR

9

I

time. It can be used for tracking and sequencing.

AVIN

10

I

Supply voltage for control circuitry. Connect to same source as PVIN.

PVIN

11, 12

I

Supply voltage for power stage. Connect to same source as AVIN.

EN

13

I

VOS

14

I

Output-voltage sense pin and connection for the control loop circuitry.

PGND

15, 16

–

Power ground

Exposed

–

Must be connected to AGND. Must be soldered to achieve appropriate power dissipation and mechanical

thermal pad

reliability.

(1)

For more information about connecting pins, see the DETAILED DESCRIPTION and APPLICATION INFORMATION sections.

(2)

An internal pulldown resistor keeps the logic level low, if pin is floating.

4

Submit Documentation Feedback

Copyright

© 2011, Texas Instruments Incorporated

Product Folder Link(s): TPS62140 TPS62141 TPS62142 TPS62143