ADC1113D125 datasheet(11/39 Pages) IDT

Part #	ADC1113D125

Description	Dual 11-bit ADC; serial JESD204A interface

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Manufacturer	IDT [Integrated Device Technology]

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ADC1113D125 4

Product data sheet

Rev. 04 — 2 July 2012

11 of 39

Integrated Device Technology

ADC1113D125

Dual 11-bit ADC; serial JESD204A interface

10.4 SPI timing

[1]

Typical values measured at VDDA =3V, VDDD =1.8 V, Tamb =25 C and CL = 5 pF. Minimum and maximum

values are across the full temperature range Tamb = 40 C to +85 C at VDDA =3V, VDDD =1.8 V;

VI (INAP, INBP)  VI (INAM,INBM) = 1 dBFS; internal reference mode; 100  differential applied to serial

outputs; unless otherwise specified.

Fig 4.

Eye diagram at 2 V receiver common-mode

005aaa089

Table 8.

SPI timing characteristics[1]

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Serial Peripheral Interface timing

tw(SCLK)

SCLK pulse width

-

40

-

ns

tw(SCLKH)

SCLK HIGH pulse

width

-16

-

ns

tw(SCLKL)

SCLK LOW pulse

width

-16

-

ns

tsu

set-up time

data to SCLK H

-

5

-

ns

CS to SCLK H

-

5

-

ns

th

hold time

data to SCLK H

-

2

-

ns

CS to SCLK H

-

2

-

ns

fclk(max)

maximum clock

frequency

-25

-

MHz

Fig 5.

SPI timing

tsu

SDIO

SCLK

R/W

W1

W0

A12

A11

D2

D1

D0

tsu

th

tw(SCLK)

005aaa065

CS

tw(SCLKL)

tw(SCLKH)

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