DAC1408D650 datasheet(11/96 Pages) IDT

Part #	DAC1408D650

Description	Dual 14-bit DAC; up to 650 Msps; 2?? 4??or 8??interpolating with JESD204A interface

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Manufacturer	IDT [Integrated Device Technology]

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DAC1408D650 6

Product data sheet

Rev. 06 — 2 July 2012

11 of 96

Integrated Device Technology

DAC1408D650

2

, 4 or 8 interpolating DAC with JESD204A

[1]

D = guaranteed by design; C = guaranteed by characterization; I = 100 % industrially tested.

[2]

Delay between the deassertion of bits FORCE_RESET_FCLK and FORCE_RESET_DCLK and the deassertion of the sync signal. It

reflects the delay required by DAC1408D650 to lock to a JESD204A stream. It supposes that the TX is already transmitting K28.5

characters in error-free conditions.

[3]

CLKINP/CLKINN inputs are at differential LVDS levels. An external termination resistor with a value of between 80

 and 120  (see

Figure 15) should be connected across the pins.

[4]

Vgpd represents the ground potential difference voltage. This is the voltage that results from current flowing through the finite resistance

and the inductance between the receiver and the driver circuit ground voltage.

[5]

Vin_p and Vin_n inputs are differential CML inputs. They are terminated internally to Vtt via 50  (see Figure 4).

[6]

SYNC_OUTP/SYNC_OUTN outputs are differential LVDS outputs. They must be terminated by a resistor with a value of between 80



and 120

.

[7]

IMD3 rejection with

6 dBFS/tone.

10. Application information

10.1 General description

The DAC1408D650 is a dual 14-bit DAC operating up to 650 Msps. With a maximum input

data rate of up to 312.5 Msps and a maximum output sampling rate of 650 Msps, the

DAC1408D650 allows more flexibility for wide bandwidth and multi-carrier systems.

Combined with its quadrature modulator and 32-bit NCO, the DAC1408D650 simplifies

the frequency selection of the system. This is also possible because of the 2

, 4 or 8

interpolation filters which remove undesired images.

DAC1408D650 supports the following JESD204A key features:

• 10-bit/8-bit decoding

• Code group synchronization

• inter-lane alignment

•

scrambling polynomial

• Character replacement

• TX/RX synchronization management via sync signals

• Multiple Converter Device Alignment-Multiple Lanes (MCDA-ML) device

DAC1408D650 can be interfaced with any logic device that features high speed SERDES

functionality. This macro is now widely available in FPGA from different vendors.

Standalone SERDES ICs can also be used.

To enhance the intrinsic board layout simplification of the JESD204A standard, IDT

includes polarity swapping for each of the lanes and additionally offers lane swapping.

Each physical lane can be configured logically as lane0, lane1, lane2 or lane3.

NSD

noise spectral density

fs =640 Msps;

4

 interpolation;

fo = 133 MHz at 0 dBFS

I-

156

-

dBm/Hz

Table 5.

Characteristics …continued

VDDA(1V8) =VDDD = 1.7 V to 1.9 V; VDDA(3V3) = 3.13 V to 3.47 V; AGND and GND are shorted together; Tamb = 40 C to

+85

C; typical values measured at VDDA(1V8) =VDDD =1.8 V; VDDA(3V3) =3.3 V; Tamb =+25 C; RL =50 ; IO(fs) =20mA;

maximum sample rate; PLL off unless otherwise specified.

Symbol

Parameter

Conditions

Test[1]

Min

Typ

Max

Unit

1x

14

x

15

++

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