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TPS51916EVM-746 Datasheet(PDF) 10 Page - Texas Instruments |
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TPS51916EVM-746 Datasheet(HTML) 10 Page - Texas Instruments |
10 / 23 page 1.48 1.49 1.5 1.51 1.52 0 2 4 6 8 10 12 14 16 18 20 I - Output Current - A O 12 Vin 20 Vin 8 Vin 8 9 10 11 12 13 14 V - Input Voltage - V I I = 0 A O 1.494 1.496 1.498 1.5 1.502 1.504 1.506 I = 20 A O Performance Data and Typical Characteristic Curves www.ti.com 7.2 DDR3 VDDQ Load Regulation Figure 5. DDR3 VDDQ Load Regulation 7.3 DDR3 VDDQ Line Regulation Figure 6. DDR3 VDDQ Line Regulation 10 Using the TPS51916EVM-746 Complete DDR2, DDR3, DDR3L, and DDR4 SLUU526 – August 2011 Memory Power Solution Synchronous Buck Controller, 2-A LDO, Buffered Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Reference |
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