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SN74LVT8996-EP Datasheet(PDF) 11 Page - Texas Instruments |
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SN74LVT8996-EP Datasheet(HTML) 11 Page - Texas Instruments |
11 / 42 page SN74LVT8996EP 3.3V 10BIT ADDRESSABLE SCAN PORT MULTIDROPADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVER SCBS764 − SEPTEMBER 2003 11 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Test-Logic-Reset The ASP TAP-state monitor powers up in the Test-Logic-Reset state. Alternatively, the ASP can be forced asynchronously to this state by assertion of its PTRST input. In the stable Test-Logic-Reset state, the ASP is enabled to receive and respond to shadow protocols. The ASP does not recognize the TSA in this state. For a target device in the stable Test-Logic-Reset state, the test logic is reset and is disabled so that the normal logic function of the device is performed. The instruction register is reset to an opcode that selects the optional IDCODE instruction, if supported, or the BYPASS instruction. Certain data registers also can be reset to their power-up values. Run-Test/Idle In the stable Run-Test/Idle state, the ASP is enabled to receive and respond to shadow protocols. The ASP does not recognize the TSA in this state. For a target device, Run-Test/Idle is a stable state in which the test logic can be actively running a test or can be idle. Select-DR-Scan, Select-lR-Scan The ASP is not enabled to receive and respond to shadow protocols in the Select-DR-Scan and Select-lR-Scan states. For a target device, no specific function is performed in the Select-DR-Scan and Select-lR-Scan states, and the TAP controller exits either of these states on the next TCK cycle. These states allow the selection of either data-register scan or instruction-register scan. Capture-DR The ASP is not enabled to receive and respond to shadow protocols in the Capture-DR state. For a target device in the Capture-DR state, the selected data register can capture a data value as specified by the current instruction. Such capture operations occur on the rising edge of TCK, upon which the Capture-DR state is exited. Shift-DR The ASP is not enabled to receive and respond to shadow protocols in the Shift-DR state. For a target device, upon entry to the Shift-DR state, the selected data register is placed in the scan path between TDI and TDO, and on the first falling edge of TCK, TDO goes from the high-impedance state to an active state. TDO outputs the logic level present in the least-significant bit of the selected data register. While in the stable Shift-DR state, data is serially shifted through the selected data register on each TCK cycle. Exit1-DR, Exit2-DR The ASP is not enabled to receive and respond to shadow protocols in the Exit1-DR and Exit2-DR states. For a target device, the Exit1-DR and Exit2-DR states are temporary states that end a data-register scan. It is possible to return to the Shift-DR state from either Exit1-DR or Exit2-DR without recapturing the data register. On the first falling edge of TCK after entry to Exit1-DR, TDO goes from the active state to the high-impedance state. Pause-DR In the stable Pause-DR state, the ASP is enabled to receive and respond to shadow protocols. Additionally, the TSA can be recognized in this state. For target devices, no specific function is performed in the stable Pause-DR state. The Pause-DR state suspends and resumes data-register scan operations without loss of data. |
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