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TLV320ADC3001IYZHR Datasheet(PDF) 8 Page - Texas Instruments |
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TLV320ADC3001IYZHR Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 81 page  WCLK BCLK DOUT t (DO-BCLK) d t (WS) d t (WS) d t f t r TLV320ADC3001 SLAS548C – OCTOBER 2008 – REVISED APRIL 2011 www.ti.com All specifications at 25 °C, DVDD = 1.8 V IOVDD = 1.8 V IOVDD = 3.3 V PARAMETER UNIT MIN MAX MIN MAX td(WS) BCLK/WCLK delay time 25 15 ns td(DO-BCLK) BCLK to DOUT delay time 25 15 ns tr Rise time 20 15 ns tf Fall time 20 15 ns NOTE: All timing specifications are measured at characterization. Figure 3. DSP Timing in Master Mode 8 Copyright © 2008–2011, Texas Instruments Incorporated |
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