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TLV5610IYZT Datasheet(PDF) 8 Page - Texas Instruments |
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TLV5610IYZT Datasheet(HTML) 8 Page - Texas Instruments |
8 / 16 page www.ti.com APPLICATION INFORMATION GENERAL FUNCTION REF CODE 0x1000 [V] (1) SERIAL INTERFACE E1 SCLK X D15 DSPMode: FS DIN SCLK FS DIN mCMode: D14 D1 D0 E15 E14 E1 E0 X X X F15 F15 X D15 D14 D1 D0 X E15 X F15 F15 E14 E0 X TLV5610IYZ SBAS389A – JULY 2006 – REVISED JULY 2006 The TLV5610IYZ is an eight-channel, 12-bit, single-supply DAC, based on a resistor string architecture. The TLV5610IYZ, a green/PB-free device, is pin-compatible with the TLV5610IYE. The TLV5610IYZ consists of a serial interface, a speed and power-down control logic, a reference input buffer, a resistor string, and a rail-to-rail output buffer. The output voltage (full-scale determined by external reference) for each channel is given by: Where: REF is the reference voltage. CODE is the digital input value. The input range is 0x000 to 0xFFF. A power on reset initially puts the internal latches to a defined state (all bits zero). A falling edge of FS starts shifting the data on DIN, starting with the MSB to the internal register on the falling edges of SCLK. After 16 bits have been transferred, the content of the shift register is moved to one of the DAC holding registers, depending on the address bits within the data word. A logic '0' on the LDAC pin is required to transfer the content of the DAC holding register to the DAC latch and to update the DAC outputs. LDAC is an asynchronous input; it can be held low if a simultaneous update of all eight channels is not needed. For daisy-chaining, DOUT provides the data sampled on DIN with a delay of 16 clock cycles. Figure 9. Timing Diagrams The differences between DSP mode (MODE = NC or 0) and µC (MODE = 1) mode: • In µC mode, FS must be held low until all 16 data bits have been transferred. If FS is driven high before the 16th falling clock edge, the data transfer is cancelled. The DAC is updated after a rising edge on FS. • In DSP mode, FS must only stay low for 20ns and can go high before the 16th falling clock edge. 8 Submit Documentation Feedback |
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