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PCA8537Q900 Datasheet(PDF) 8 Page - NXP Semiconductors |
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PCA8537Q900 Datasheet(HTML) 8 Page - NXP Semiconductors |
8 / 82 page PCA8537 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 1 — 31 May 2012 8 of 82 NXP Semiconductors PCA8537 Automotive LCD driver for multiplex rates up to 1:8 8.1.1 Command: Initialize This command generates a chip-wide reset which resets all command values to their default values. After this command is sent, it is possible to send additional commands without the need to re-initialize the interface. The reset takes 100 ns to complete. 8.1.2 Command: OTP-refresh During production and testing of the device, each IC is calibrated to achieve the specified accuracy of VLCD, the frame frequency, and the temperature measurement. This calibration is performed on EPROM cells called One Time Programmable (OTP) cells. The device reads these cells every time at power-on, after a reset, and every time when the initialize command or the OTP-refresh command is sent. Remark: It is recommended not to enter power-down mode during the OTP refresh cycle. 8.1.3 Command: Oscillator-ctrl The Oscillator-ctrl command switches between internal and external oscillator and enables or disables the pin CLK. [1] Default value. 8.1.3.1 Oscillator The internal logic and LCD drive signals of the PCA8537 are timed either by the built-in oscillator or from an external clock. Table 5. Initialize - initialize command bit description For further information, see Section 8.2 on page 17. Bit Symbol Binary value Description 7 to 0 - 00111010 fixed value Table 6. OTP-refresh - OTP-refresh command bit description Bit Symbol Binary value Description 7 to 0 - 11010000 fixed value Table 7. Oscillator-ctrl - oscillator control command bit description For further information, see Section 8.1.3.1. Bit Symbol Binary value Description 7 to 2 - 110011 fixed value 1COE control pin CLK 0[1] clock signal not available on pin CLK; pin CLK is in 3-state and may be left floating 1 clock signal available on pin CLK 0OSC oscillator source 0[1] internal oscillator used 1 external oscillator used; pin CLK becomes an input |
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