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TLV70018QDDCRQ1 Datasheet(PDF) 11 Page - Texas Instruments |
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TLV70018QDDCRQ1 Datasheet(HTML) 11 Page - Texas Instruments |
11 / 19 page P =(V V ) I - ´ D IN OUT OUT TLV70018-Q1 TLV70012-Q1 www.ti.com SLVSB67A – NOVEMBER 2011 – REVISED MARCH 2012 As with any linear regulator, PSRR and transient The internal protection circuitry of the TLV70018-Q1 response are degraded as (VIN – VOUT) approaches has been designed to protect against overload dropout. This effect is shown in Figure 15 in the conditions. It was not intended to replace proper Typical Characteristics section. heatsinking. Continuously running the TLV70018-Q1 into thermal shutdown degrades device reliability. TRANSIENT RESPONSE POWER DISSIPATION As with any regulator, increasing the size of the output capacitor reduces over-/undershoot magnitude The ability to remove heat from the die is different for but increases the duration of the transient response. each package type, presenting different considerations in the printed circuit board (PCB) layout. The PCB area around the device that is free UNDERVOLTAGE LOCKOUT (UVLO) of other components moves the heat from the device The TLV70018-Q1 uses an undervoltage lockout to the ambient air. circuit to keep the output shut off until internal Thermal performance data for TLV70018-Q1 were circuitry is operating properly. gathered using the TLV700 evaluation module (EVM), a 2-layer board with two ounces of copper per side. THERMAL INFORMATION The dimensions and layout for the SOT23-5 (DBV) Thermal protection disables the output when the EVM are shown in Figure 25 and Figure 26. junction temperature rises to approximately +165°C, Corresponding thermal performance data are given in allowing the device to cool. When the junction Table 1. Note that this board has provision for temperature cools to approximately +145°C, the soldering not only the SOT23-5 package on the output circuitry is again enabled. Depending on power bottom layer, but also the SC-70 package on the top dissipation, thermal resistance, and ambient layer. Corresponding thermal performance data is temperature, the thermal protection circuit may cycle again given in Table 1. Using heavier copper on and off. This cycling limits the dissipation of the increases the effectiveness in removing heat from the regulator, protecting it from damage as a result of device. The addition of plated through-holes to heat- overheating. dissipating layers also improves heatsink effectiveness. Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an Power dissipation depends on input voltage and load inadequate heatsink. For reliable operation, junction conditions. Power dissipation (PD) is equal to the temperature should be limited to +125°C maximum. product of the output current and the voltage drop across the output pass element, as shown in To estimate the margin of safety in a complete design Equation 1. (including heatsink), increase the ambient temperature until the thermal protection is triggered; (1) use worst-case loads and signal conditions. PACKAGE MOUNTING Solder pad footprint recommendations for the TLV70018-Q1 are available from the Texas Instruments web site at www.ti.com. Table 1. EVM Dissipation Ratings DERATING PACKAG FACTOR ABOVE BOARD E RθJC RθJA TA = 25°C TA ≤ 25°C TA = 70°C TA = 85°C TA = 125°C Low-K(1) DDC 90°C/W 280°C/W 3.6 mW/°C 360 mW 200 mW 145 mW 51 mW High-K(2) DDC 90°C/W 200°C/W 5.0 mW/°C 500 mW 275 mW 200 mW 106 mW (1) The JEDEC low-K (1s) board used to derive this data was a 3-inch × 3-inch, two-layer board with 2-ounce copper traces on top of the board. (2) The JEDEC high-K (2s2p) board used to derive this data was a 3-inch × 3-inch, multilayer board with 1-ounce internal power and ground planes and 2-ounce copper traces on top and bottom of the board. Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Link(s): TLV70012-Q1 |
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