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TMS470R1VC346APZ-T Datasheet(PDF) 1 Page - Texas Instruments |
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TMS470R1VC346APZ-T Datasheet(HTML) 1 Page - Texas Instruments |
1 / 54 page Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Code Composer Studio is a trademark of Texas Instruments. ARM7TDMI is a trademark of Advanced RISC Machines (ARM) Limited. All trademarks are the property of their respective owners. † The test-access port is compatible with the IEEE Standard 1149.1-1990, IEEE Standard Test-Access Port and Boundary Scan Architecture specification. Boundary scan is not supported on this device. TMS470R1VC336,TMS470R1VC346 16/32-BIT RISC ROM MICROCONTROLLERS SPNS084E – MAY 2003 – REVISED AUGUST 2006 1 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443 Copyright © 2006, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. High-Performance Static CMOS Technology TMS470R1x 16/32-Bit RISC Core (ARM7TDMI ™) – 24-MHz System Clock (VC346 only) – 28-MHz System Clock (VC336 only) – 48-MHz Pipeline Mode – Independent 16/32-Bit Instruction Set – Open Architecture With Third-Party Support – Built-In Debug Module – Utilizes Big-Endian Format Integrated Memory – 128K-Byte Program ROM – ROM Pipeline Wrapper (RPW) – 8K-Byte Static RAM (SRAM) Operating Features – Core Supply Voltage (VCC): 1.81 V - 2.06 V – Core Supply Voltage (VCC): 1.70 V - 2.06 V When Used At or Below 85C Ambient Temp and 115C Junction Temp – I/O Supply Voltage (VCCIO): 3.0 V - 3.6 V – Low-Power Modes: STANDBY and HALT – Industrial and Automotive Temperature Ranges 470+ System Module – 32-Bit Address Space Decoding – Bus Supervision for Memory and Peripherals – Analog Watchdog (AWD) Timer – Real-Time Interrupt (RTI) – System Integrity and Failure Detection Zero-Pin Phase-Locked Loop (ZPLL)-Based Clock Module With Prescaler – Multiply-by-4 or -8 Internal ZPLL Option – ZPLL Bypass Mode Six Communication Interfaces: – Two Serial Peripheral Interfaces (SPIs) – 255 Programmable Baud Rates – Two Serial Communications Interfaces (SCIs) –224 Selectable Baud Rates – Asynchronous/Isosynchronous Modes – Standard CAN Controller (SCC) – 16-Mailbox Capacity – Fully Compliant With CAN Protocol, Version 2.0B – Class II Serial Interface (C2SIa) – Two Selectable Data Rates – Normal Mode 10.4 Kbps and 4X Mode 41.6 Kbps High-End Timer (HET) – 27 Programmable I/O Channels (VC336): – 23 High-Resolution Pins – 4 Standard-Resolution Pins – 16 Programmable I/O Channels (VC346): – 14 High-Resolution Pins – 2 Standard-Resolution Pins – High-Resolution Share Feature (XOR) – HET RAM (64-Instruction Capacity) 10-Bit Multi-Buffered ADC (MibADC) 12-Channel (VC336), 16-Channel (VC346) –64-Word FIFO Buffer – Single- or Continuous-Conversion Modes –1.55 μs Minimum Sample and Conversion Time – Calibration Mode and Self-Test Features Eight External Interrupts (VC346) Six External Interrupts (VC336) Flexible Interrupt Handling 5 Dedicated General-Purpose I/O (GIO) Pins, 1 Input-Only GIO Pin, and 48 Additional Peripheral I/Os (VC336) 11 Dedicated GIO Pins,1 Input-Only GIO Pin, and 38 Additional Peripheral I/Os (VC346) External Clock Prescale (ECP) Module – Programmable Low-Frequency External Clock (CLK) On-Chip Scan-Base Emulation Logic, IEEE Standard 1149.1† (JTAG) Test-Access Port 100-Pin Plastic Low-Profile Quad Flatpack (PZ Suffix) Development System Support Tools Available – Code Composer Studio ™ Integrated Development Environment (IDE) – HET Assembler and Simulator – Real-Time In-Circuit Emulation |
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