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TPS3897PDRYR Datasheet(PDF) 5 Page - Texas Instruments |
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TPS3897PDRYR Datasheet(HTML) 5 Page - Texas Instruments |
5 / 21 page V (POR) UVLO t pd(r) t d(OFF) t pd(f) V IT+ V IT+ t pd(r) t d(P) V V - IT+ hys VCC SENSE ENABLE SENSE_OUT GND VCC ENABLE (1) SENSE SENSE_OUT ENABLE GND TPS3895 DSP, CPU, or FPGA VCC R1 R2 3.3V CT 0.1 F m See Note (2) TPS3895, TPS3896 TPS3897, TPS3898 www.ti.com SBVS172A – JULY 2011 – REVISED SEPTEMBER 2011 Figure 4. TPS3896P/TPS3898P Timing TYPICAL APPLICATION (1) ENABLE can also be driven with a separate 1.5-V or greater power supply. (2) Capacitor is optional. If capacitor not used, leave CT pin open for 40- µs delay. Figure 5. TPS3895 Typical Application Copyright © 2011, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Link(s): TPS3895 TPS3896 TPS3897 TPS3898 |
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