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SST34HF1641 Datasheet(PDF) 7 Page - Silicon Storage Technology, Inc

Part # SST34HF1641
Description  16 Mbit Concurrent SuperFlash 2 / 4 Mbit SRAM ComboMemory
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Manufacturer  SST [Silicon Storage Technology, Inc]
Direct Link  http://www.sst.com/
Logo SST - Silicon Storage Technology, Inc

SST34HF1641 Datasheet(HTML) 7 Page - Silicon Storage Technology, Inc

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Data Sheet
16 Mbit Concurrent SuperFlash + 2 / 4 Mbit SRAM ComboMemory
SST34HF1621 / SST34HF1641
7
©2001 Silicon Storage Technology, Inc.
S71172-05-000
10/01 523
FIGURE 2: PIN ASSIGNMENTS FOR 56-BALL LFBGA (8MM X 10MM) COMBOMEMORY PINOUT
TABLE
2: PIN DESCRIPTION
Symbol
Pin Name
Functions
AMS1 to A0
1. AMS = Most Significant Address
Address Inputs
To provide flash address, A19-A0.
To provide SRAM address, A16-A0 for 2M and A17-A0 for 4M
SA
Address Input (SRAM)
To provide SRAM address input in byte mode (x8). When CIOs is VIL, the SRAM is in
Byte mode and SA provides the most significant address input. When CIOs is VIH, the
SRAM is in Word mode and SA becomes a Don’t Care pin.
DQ15-DQ0 Data Inputs/Outputs
To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a flash Erase/Program cycle. The outputs are in
tri-state when OE# is high or BES1# is high or BES2 is low and BEF# is high.
BEF#
Flash Memory Bank Enable
To activate the Flash memory bank when BEF# is low
BES1#
SRAM Memory Bank Enable To activate the SRAM memory bank when BES1# is low
BES2
SRAM Memory Bank Enable To activate the SRAM memory bank when BES2 is high
OE#
Output Enable
To gate the data output buffers
WE#
Write Enable
To control the Write operations
UBS#
Upper Byte Control (SRAM)
To enable DQ15-DQ8
LBS#
Lower Byte Control (SRAM)
To enable DQ7-DQ0
CIOs
I/O Configuration (SRAM)
CIOs = VIH is Word mode (x16), CIOs = VIL is Byte mode (x8)
WP#
Write Protect
To protect and unprotect sectors from Erase or Program operation
RST#
Reset
To Reset and return the device to Read mode
RY/BY#
Ready/Busy#
To output the status of a Program or Erase Operation
RY/BY# is a open drain output, so a 10K
Ω - 100KΩ pull-up resistor is required to
allow RY/BY# to transition high indicating the device is ready to read.
VSS
Ground
VDDF
Power Supply (Flash)
2.7-3.3V Power Supply to Flash only
VDDS
Power Supply (SRAM)
2.7-3.3V Power Supply to SRAM only
NC
No Connection
Unconnected pins
T2.5 523
523 56-lfbga ILL P01.2
A11
A8
WE#
WP#
LBS#
A7
A15
A12
A19
BES2
RST#
UBS#
A6
A3
NC
A13
A9
NC
RY/BY#
A18
A5
A2
NC
A14
A10
A17
A4
A1
A16
SA
DQ6
DQ1
VSS
A0
NC
DQ15
DQ13
DQ4
DQ3
DQ9
OE#
BEF#
VSS
DQ7
DQ12
VDDS
VDDF
DQ10
DQ0
BES1#
DQ14
DQ5
CIOs
DQ11
DQ2
DQ8
A B C D E F G H
SST34HF1621/1641
8
7
6
5
4
3
2
1
TOP VIEW (balls facing down)


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