HS-565BRH, HS-565BEH

5

FN4607.4

May 7, 2012

Settling Time

This is a challenging measurement, in which the result depends

on the method chosen, the precision and quality of test

equipment and the operating configuration of the DAC (test

conditions). As a result, the different techniques in use by

converter manufacturers can lead to consistently different

results. An engineer should understand the advantage and

limitations of a given test method before using the specified

settling time as a basis for design.

The approach used for several years at Intersil calls for a strobed

comparator to sense final perturbations of the DAC output

waveform. This gives the LSB a reasonable magnitude (814mV)

for the HS-565BRH, HS-565BEH, which provides the comparator

with enough overdrive to establish an accurate

±0.50 LSB

window about the final settled value. Also, the required test

conditions simulate the DACs environment for a common

application - use in a successive approximation A/D converter.

Considerable experience has shown this to be a reliable and

repeatable way to measure settling time.

The usual specification is based on a 10V step, produced by

simultaneously switching all bits from off-to-on (tON) or on-to-off

(tOFF). The slower of the two cases is specified, as measured

from 50% of the digital input transition to the final entry within a

window of ±0.50 LSB about the settled value. Four

measurements characterize a given type of DAC:

(Cases (b) and (c) may be eliminated unless the overshoot

exceeds 0.50 LSB). For example, refer to Figures 4A and 4B for

the measurement of case (d).

Procedure

As shown in Figure 4B, settling time equals tX plus the

comparator delay (tD = 15ns). To measure tX,

• Adjust the delay on generator number 2 for a tX of several

microseconds. This assures that the DAC output has settled to

its final wave.

• Switch on the LSB (+5V)

• Adjust the VLSB supply for 50% triggering at COMPARATOR

OUT. This is indicated by traces of equal brightness on the

oscilloscope display as shown in Figure 4B. Note DVM reading.

•Switch to LSB to Pulse (P)

• Readjust the VLSB supply for 50% triggering as before, and

note DVM reading. One LSB equals one tenth the difference in

the DVM readings noted above.

• Adjust the VLSB supply to reduce the DVM reading by 5 LSBs

(DVM reads 10X, so this sets the comparator to sense the final

settled value minus 0.50 LSB). Comparator output disappears.

• Reduce generator number 2 delay until comparator output

reappears, and adjust for “equal brightness”.

• Measure tX from scope as shown in Figure 4B. Settling time

equals tX + tD, i.e., tX + 15ns.

(a) tON, to final value +0.50 LSB

(b) tON, to final value -0.50 LSB

(c)

tOFF, to final value +0.50 LSB

(d) OFF, to final value -0.50 LSB

TABLE 1. OPERATING MODES AND CALIBRATION

MODE

CIRCUIT CONNECTIONS

CALIBRATION

OUTPUT

RANGE

PIN 10

TO

PIN 11

TO

RESISTOR

(R)

APPLY

INPUT CODE

ADJUST

TO SET VO

Unipolar (See Figure 2)

0 to +10V

VO

Pin 10

1.43k

All 0’s

All 1’s

R1

R2

0V

+9.99756V

0 to +5V

VO

Pin 9

1.1k

All 0’s

All 1’s

R1

R2

0V

+4.99878V

Bipolar (See Figure 3)

±10V

NC

VO

1.69k

All 0’s

All 1’s

R3

R4

-10V

+9.99512V

±5V

VO

Pin 10

1.43k

All 0’s

All 1’s

R3

R4

-5V

+4.99756V

±2.5V

VO

Pin 9

1.1k

All 0’s

All 1’s

R3

R4

-2.5V

+2.49878V